Impact of self-heating in SOI FinFETs on analog circuits and interdie variability

IEEE Electron Device Letters

Volumn 32, Issue 3, 2011, Pages 249-251

  Monga, Udit ^a   Aghassi, Jasmin ^b   Siprak, Domagoj ^b   Sedlmeir, Josef ^b   Hanke, Christian ^b   Kubrak, Volker ^b   Heinrich, Roland ^b   Fjeldly, Tor A ^a  

^a NORWEGIAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Norway)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

Interdie variability; nonisothermal conductances; self heating (SH); SOI FinFETs

Indexed keywords

ANALOG DESIGN; EXPERIMENTAL EVALUATION; INTERDIE VARIABILITY; LONG CHANNEL DEVICES; LOW FREQUENCY; LOWER FREQUENCIES; NONISOTHERMAL; OUTPUT CONDUCTANCE; P-TYPE; S-PARAMETER MEASUREMENTS; SELF-HEATING; SOI FINFETS;

ANALOG CIRCUITS; INTEGRATED CIRCUITS; SCATTERING PARAMETERS;

HEATING;

EID: 79951955861     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2010.2097235     Document Type: Article

References (10)

1. S. H. Tang, L. Chang, N. Lindert, Y.-K. Choi, W.-C. Lee, X. Huang, V. Subramanian, J. Bokor, T.-J. King, and C. Hu, "FinFET-A quasiplanar double-gate MOSFET," in Proc. ISSCC, 2001, pp. 118-119.
2. S. Zimin, L. Litian, and L. Zhijian, "Self-heating effect in SOI MOSFETs," in Proc. ICSICT, 1998, pp. 572-574.
3. B. M. Tenbroek, M. S. L. Lee, W. Redman-White, R. J. T. Bunyan, and M. J. Uren, "Impact of self-heating and thermal coupling on analog circuits in SOI CMOS," IEEE J. Solid-State Circuits, vol. 33, no. 7, pp. 1037-1046, Jul. 1998. (Pubitemid 128566790)
4. B. M. Tenbroek, M. S. L. Lee, W. Redman-White, R. J. T. Bunyan, and M. J. Uren, "Self heating effects in SOI MOSFETS and their measurement by small signal conductance techniques," IEEE Trans. Electron Devices, vol. 43, no. 12, pp. 2240-2248, Dec. 1996. (Pubitemid 126775639)
5. D. Vasileska, K. Raleva, and S. M. Goodnick, "Self-heating effects in nanoscale FD SOI devices: The role of the substrate, boundary conditions at various interfaces, and the dielectric material type for the box," IEEE Trans. Electron Devices, vol. 56, no. 12, pp. 3064-3071, Dec. 2009.
6. E. Pop, R. Dutton, and K. Goodson, "Thermal analysis of ultra-thin body device scaling," in IEDM Tech. Dig., 2003, pp. 36.6.1-36.6.4.
7. W. Molzer, T. Schulz, W. Xiong, R. C. Cleavelin, K. Schrüfer, A. Marshall, K. Matthews, J. Sedlmeir, D. Siprak, G. Knoblinger, L. Bertolissi, P. Patruno, and J.-P. Colinge, "Self heating simulation of multi-gate FETs," in Proc. IEEE ESSDERC, 2006, pp. 311-314.
8. A. J. Scholten, G. D. J. Smit, R. M. T. Pijper, L. F. Tiemeijer, H. P. Tuinhout, J.-L. P. J. van der Steen, A. Mercha, M. Braccioli, and D. B. M. Klaassen, "Experimental assessment of self-heating in SOI FinFETs," in IEDM Tech. Dig., 2009, pp. 305-308.
9. K. von Arnim, E. Augendre, A. C. Pacha, T. Schulz, K. T. San, F. Bauer, A. Nackaerts, R. Rooyackers, T. Vandeweyer, B. Degroote, N. Collaert, A. Dixit, R. Singanamalla, W. Xiong, A. Marshall, C. R. Cleavelin, K. Schrufer, and M. Jurczak, "Low-power multi-gate FET CMOS technology with 13.9 ps inverter delay, large-scaled integrated high performance digital circuits and SRAM," in VLSI Symp. Tech. Dig., 2007, pp. 106-107.
10. N. Rinaldi, "Small-signal operation of semiconductor devices including self-heating, with application to thermal characterization and instability analysis," IEEE Trans. Electron Devices, vol. 48, no. 2, pp. 323-331, Feb. 2001. (Pubitemid 32254557)