Direct contact of high-k/Si gate stack for EOT below 0.7 nm using LaCe-silicate layer with Vfb controllability

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2010, Pages 69-70

  Kakushima, K ^a   Koyanagi, T ^a   Kitayama, D ^a   Kouda, M ^a   Song, J ^a   Kawanago, T ^a   Mamatrishat, M ^a   Tachi, K ^a   Bera, M K ^a   Ahmet, P ^a   Nohira, H ^b   Tsutsui, K ^a   Nishiyama, A ^a   Sugii, N ^a   Natori, K ^a   Hattori, T ^a   Yamada, K ^c   Iwai, H ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^b TOKYO CITY UNIVERSITY   (Japan)

^c WASEDA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPOSITIONAL RATIO; DIELECTRIC CONSTANTS; DIRECT CONTACT; FLAT-BAND VOLTAGE; GATE OXIDE; GATE STACKS; GATE-LEAKAGE CURRENT; GE ATOM; SILICATE LAYERS;

GATE DIELECTRICS; GERMANIUM; LEAKAGE CURRENTS; LOGIC GATES;

SILICATES;

EID: 77957861958     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2010.5556115     Document Type: Conference Paper

References (4)

1. ITRS 2008 update.
2. M. Takahashi, et al., IEDM, p. 523 (2007).
3. T. Ando, et al., IEDM, p. 423 (2009).
4. K. Kakushima, et al., ESSDERC, p.126 (2008).