Design for reliability in via middle and via last 3-D chipstacks incorporating TSVs

2010 12th Electronics Packaging Technology Conference, EPTC 2010

Volumn , Issue , 2010, Pages 328-332

  Trigg, A D ^a   Yu, Li Hong ^a   Zhong, Xiong Yong ^a   Lin, Shi Jing ^a   Kuo, Cheng Cheng ^a   Khan, Navas ^a   Hwa, Teo Keng ^a   Shan, Gao ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE DEVICES; CMOS PROCESSS; DESIGN FOR RELIABILITY; MICRO-BUMPS; MOISTURE INGRESS; TEST CHIPS; TEST STRUCTURE; THERMAL PERFORMANCE; THROUGH SILICON VIAS;

CMOS INTEGRATED CIRCUITS; ELECTRONIC EQUIPMENT MANUFACTURE; RELIABILITY; TECHNOLOGY; THREE DIMENSIONAL;

CHIP SCALE PACKAGES;

EID: 79951882560     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2010.5702657     Document Type: Conference Paper

References (10)

1. Xiaowu Zhang et al, "Development of Through Silicon Via (TSV) Interposer Technology for Large Die (21x21mm) Fine-pitch Cu/low-k FCBGA Package", Proc 59th Electronic Components and Technology Conf, San Diego CA 2009, pp 305-312.
2. Aibin Yu, "Three Dimensional Interconnects with High Aspect Ratio TSVs and Fine Pitch Solder Microbumps", Proc 59th Electronic Components and Technology Conf, San Diego CA 2009, pp 350-354.
3. Srinivasa Rao Vempati et al, "Development of 3-D Silicon Die Stacked Package Using Flip Chip Technology with Micro Bump Interconnects", Proc 59th Electronic Components and Technology Conf, San Diego CA 2009, pp 980-987.
4. IME & EDB Press Release "A*STAR and EDB launch 3-dimensional through-silicon via consortium to boost next generation wafer manufacturing capability for singapore semiconductor industry", Issued 8 September 2009
5. A D Trigg et al, "Design and Fabrication of a Reliability Test Chip for 3D-TSV" Proc 60th Electronic Components and Technology Conf, Las Vegas, USA 2010, pp 79-83, 2010
6. 3D Chip Stack With Through-Silicon Vias (TSVS): Identifying, Evaluating and Understanding Reliability Interactions JEDEC Document JEP158, November 2009
7. C S. Selvanayagam et al, "Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via)and their Flip-Chip Microbumps", Proc 58th Electronic Components and Technology Conf, Miami, USA, pp 1073-1081
8. C. Okoro et al," Extraction of the Appropriate Material Property for Realistic Modeling of Through-Silicon-Vias using μ-Raman Spectroscopy", Proc. Interconnect Technology Conference IITC 2008, Burlingame, CA, USA.pp 16-18, 2008
9. Xi Liu et al,"Failure Mechanisms and Optimum Design for Electroplated Copper Through-Silicon Vias (TSV)", Proc 59th Electronic Components and Technology Conf, San Diego CA 2009, pp 624-629
10. P Garrou, "Researchers Strive for Copper TSV Reliability", Semiconductor International, 3 December 2009.