-
2
-
-
75649121827
-
Practical strategies for power-efficient computing technologies
-
Feb.
-
L. Chang et al., "Practical Strategies for Power-Efficient Computing Technologies," Proc. IEEE, vol. 98, no. 2, pp. 215-236, Feb. 2010.
-
(2010)
Proc. IEEE
, vol.98
, Issue.2
, pp. 215-236
-
-
Chang, L.1
-
3
-
-
75649093754
-
Near-threshold computing: Reclaiming moore's law through energy efficient integrated circuits
-
Feb.
-
R. Dreslinski, M. Wiekowski, D. Blaauw, D. Sylvester, and T. Mudge, "Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits," Proc. IEEE, vol. 98, no. 2, pp. 253-266, Feb. 2010.
-
(2010)
Proc. IEEE
, vol.98
, Issue.2
, pp. 253-266
-
-
Dreslinski, R.1
Wiekowski, M.2
Blaauw, D.3
Sylvester, D.4
Mudge, T.5
-
4
-
-
0025415048
-
Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
-
DOI 10.1109/4.52187
-
T. Sakurai and R. Newton, "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas," IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584-594, April 1990. (Pubitemid 20701405)
-
(1990)
IEEE Journal of Solid-State Circuits
, vol.25
, Issue.2
, pp. 584-594
-
-
Sakurai Takayasu1
Newton A.Richard2
-
5
-
-
0023401686
-
BSIM: BERKELEY SHORT-CHANNEL IGFET MODEL FOR MOS TRANSISTORS.
-
B. Sheu, D. Sharfetter, P, Ko, and M. Jeng, "BSIM: Berkeley Short-Channel IGFET Model for MOS Transistors," IEEE J. Solid-State Circuits, vol. SC-22, no. 4, pp. 558-566, Aug. 1987. (Pubitemid 17631990)
-
(1987)
IEEE Journal of Solid-State Circuits
, vol.SC-22
, Issue.4
, pp. 558-566
-
-
Sheu Bing, J.1
Scharfetter Donald, L.2
Ko Ping-Keung3
Jeng Min-Chie4
-
6
-
-
25144514874
-
Modeling and sizing for minimum energy operation in subthreshold circuits
-
Sept.
-
B. Calhoun, A. Wang, and A. Chandrakasan, "Modeling and Sizing for Minimum Energy Operation in Subthreshold Circuits," IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1778-1786, Sept. 2005.
-
(2005)
IEEE J. Solid-State Circuits
, vol.40
, Issue.9
, pp. 1778-1786
-
-
Calhoun, B.1
Wang, A.2
Chandrakasan, A.3
-
8
-
-
0033722287
-
A minimum total power methodology for projecting limits on CMOS GSI
-
June
-
A. Bhavnagarwala, B. Austin, K. Bowman, and J. Meindl, "A Minimum Total Power Methodology for Projecting Limits on CMOS GSI," IEEE Trans. VLSI, vol. 8, no. 3, pp. 235-251, June 2000.
-
(2000)
IEEE Trans. VLSI
, vol.8
, Issue.3
, pp. 235-251
-
-
Bhavnagarwala, A.1
Austin, B.2
Bowman, K.3
Meindl, J.4
-
9
-
-
0029342165
-
An analyitical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications
-
July
-
C. Enz, F. Krummenacher, and E. Vittoz, "An Analyitical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Applications," Analog Integrated Circuits and Signal Processing, vol. 8, no. 1, pp. 83-114, July 1995.
-
(1995)
Analog Integrated Circuits and Signal Processing
, vol.8
, Issue.1
, pp. 83-114
-
-
Enz, C.1
Krummenacher, F.2
Vittoz, E.3
-
10
-
-
75649141765
-
Ultralow-power design in near-threshold region
-
Feb.
-
D. Marković, C. Wang, L. Alarcón, T. Liu, and J. Rabaey, "Ultralow-Power Design in Near-Threshold Region," Proc. IEEE, vol. 98, no. 2, pp. 237-252, Feb. 2010.
-
(2010)
Proc. IEEE
, vol.98
, Issue.2
, pp. 237-252
-
-
Marković, D.1
Wang, C.2
Alarcón, L.3
Liu, T.4
Rabaey, J.5
-
11
-
-
21644436688
-
High performance and low power transistors integrated in 65nm bulk CMOS technology
-
Z. Luo, et al., "High Performance and Low Power Transistors Integrated in 65nm Bulk CMOS Technology," IEEE Intl. Electron Devices Meeting, pp. 28.3.1-28.3.4, 2004.
-
(2004)
IEEE Intl. Electron Devices Meeting
, pp. 2831-2834
-
-
Luo, Z.1
-
13
-
-
0036923355
-
The effective drive current in CMOS inverters
-
M. Na, E. Nowak, W. Haensch, and J. Cai, "The Effective Drive Current in CMOS Inverters," Proc. Intl. Electron Dev. Meet, 2002, pp. 121-124.
-
(2002)
Proc. Intl. Electron Dev. Meet
, pp. 121-124
-
-
Na, M.1
Nowak, E.2
Haensch, W.3
Cai, J.4
-
14
-
-
33748524600
-
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling
-
DOI 10.1109/TVLSI.2005.859588
-
B. Zhai, D. Blaauw, D. Sylvester, and K. Flautner, "The Limit of Dynamic Voltage Scaling and Insomniac Dynamic Voltage Scaling," IEEE Trans. VLSI, vol. 13, no. 11, pp. 1239-1252, Nov. 2005. (Pubitemid 46395318)
-
(2005)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, vol.13
, Issue.11
, pp. 1239-1252
-
-
Zhai, B.1
Blaauw, D.2
Sylvester, D.3
Flautner, K.4
-
15
-
-
28444444598
-
Analysis and mitigation of variability in subthreshold design
-
ISLPED'05 - Proceedings of the 2005 International Symposium on Low Power Electronics and Design
-
B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, "Analysis and Mitigation of Variaiblity in Subthreshold Design," Intl. Symp. Low Power Electronics and Design, 2005, pp. 20-25. (Pubitemid 41731619)
-
(2005)
Proceedings of the International Symposium on Low Power Electronics and Design
, pp. 20-25
-
-
Zhai, B.1
Hanson, S.2
Blaauw, D.3
Sylvester, D.4
|