Multi-processor system-level synthesis for multiple applications on platform FPGA

Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2007, Pages 92-97

  Kumar, Akash ^a,b   Fernando, Shakith ^b   Ha, Yajun ^b   Mesman, Bart ^a   Corporaal, Henk ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATIONS; DESIGN; FAULT TOLERANCE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUITS; MULTIPROCESSING SYSTEMS; QUALITY ASSURANCE; RELIABILITY; SPACE RESEARCH;

ABSTRACTION LEVELS; APPLICATION DESIGNS; CASE STUDIES; DESIGN METHODOLOGIES; DESIGN POINTS; DESIGN SPACE EXPLORATIONS; JPEG DECODERS; MODERN EMBEDDED SYSTEMS; MULTIPLE APPLICATIONS; MULTIPROCESSOR SYSTEMS; ON CHIPS; PROCESSOR SYSTEMS;

EMBEDDED SYSTEMS;

EID: 48149093478     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2007.4380631     Document Type: Conference Paper

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