On signalling over Through-Silicon Via (TSV) interconnects in 3-D integrated circuits

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2010, Pages 1325-1328

  Weerasekera, Roshan ^a   Grange, Matt ^a   Pamunuwa, Dinesh ^a   Tenhunen, Hannu ^b  

^a LANCASTER UNIVERSITY   (United Kingdom)

^b ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

DATA REDUCTION; ELECTRONICS PACKAGING; ENERGY UTILIZATION; INTEGRATED CIRCUIT INTERCONNECTS; SILICON; TIMING CIRCUITS;

3-D INTEGRATED CIRCUIT; 3D INTEGRATED CIRCUIT (ICS); ELECTRICAL MODELING; PARASITIC COMPONENTS; PERFORMANCE METRICS; SIGNAL INTEGRITY; SPICE SIMULATIONS; THROUGH-SILICON-VIA (TSV);

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 77953116301     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2010.5457013     Document Type: Conference Paper

References (11)

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