Optimal Design of Clock Trees for Multigigahertz Applications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 3, 2004, Pages 329-345

  Escovar, Rafael ^a   Suaya, Roberto ^a  

^a MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

Circuit optimization; Clocks; Delay estimation; Inductance

Indexed keywords

CAPACITANCE; CLOCKS; COMPUTATIONAL COMPLEXITY; ELECTRIC LOADS; ELECTRIC VARIABLES MEASUREMENT; GIBBS FREE ENERGY; INDUCTANCE; NONLINEAR EQUATIONS; PARAMETER ESTIMATION; PROBLEM SOLVING; SIGNAL PROCESSING; SPEED; TRANSMISSION LINE THEORY; TREES (MATHEMATICS);

CIRCUIT OPTIMIZATION; DELAY ESTIMATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 1642386901     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.823350     Document Type: Article

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