An on-chip delay- and skew-insensitive multi-cycle communication scheme

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Caputa, Peter ^a   Svensson, Christer ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUIT TRACKING; LEAKAGE CURRENTS; LOGIC DESIGN; LOGIC GATES; TELECOMMUNICATION NETWORKS;

CIRCUIT OPERATION; NOISE MARGIN; OVERHEAD KEEPER CIRCUIT; PVT TRACKING;

ELECTRIC DELAY LINES;

EID: 39749165279     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. P. Cocchini, "A Methodology for Optimal Repeater Insertion in Pipelined Interconnects," IEEE Trans. Computer-Aided Design, vol. 22, pp. 1613-1624, 2003.
2. R McInerney, et al., "Methodology for Repeater Insertion Management in the RTL, Layout, Floorplan and Fullchip Timing Databases of the Itanium Microprocessor," Proc. Int'l. Symp. Physical Design, pp. 99-104, 2000.
3. A. Edman and C. Svensson, "Timing Closure through a Globally Synchronous, Timing Partitioned Design Methodology," Proc of Design Automation Conference, pp. 71-74, 2004.
4. P. Caputa and C. Svensson, "Well-Behaved Global On-Chip Interconnect," IEEE Trans. Circuits Syst. I: vol. 52, no. 2, pp. 318-323, 2005.
5. http://cmp.imag.fr/products/ic/?p=STHCMOS8, June, 2005