Automated transistor sizing for FPGA architecture exploration

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 792-795

  Kuon, Ian ^a   Rose, Jonathan ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

FPGA; Optimization; Transistor sizing

Indexed keywords

ARCHITECTURE; AUTOMATION; COMPUTER AIDED DESIGN; COMPUTER NETWORKS; DIGITAL INTEGRATED CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INDUSTRIAL ENGINEERING; MATHEMATICAL TECHNIQUES; SYSTEMS ANALYSIS;

FPGA; LEVEL DESIGN; OPTIMIZATION; TRANSISTOR SIZING;

ARCHITECTURAL DESIGN;

EID: 51549109187     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555927     Document Type: Conference Paper

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