Lowering the latency of interfaces for rationally-related frequencies

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2010, Pages 23-30

  Chabloz, Jean Michel ^a   Hemani, Ahmed ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK CYCLES; COMPUTATION TIME; DESIGN PARADIGM; DESIGN STYLES; MESOCHRONOUS; MULTI FREQUENCY; PERFORMANCE PENALTIES; SYNCHRONOUS INTERFACE;

DESIGN;

EID: 78650752605     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2010.5647563     Document Type: Conference Paper

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