Islands of synchronicity, a design methodology for SoC design

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 3, Issue , 2004, Pages 64-69

  Niranjan, A P ^a   Wiscombe, Paul ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN COMPLEXITY; DESIGN METHODOLOGY; MICRON TECHNOLOGIES; PHYSICAL DESIGN; SOC IMPLEMENTATION; SYSTEM ON CHIP DESIGN; TIME TO MARKET; TIMING CLOSURES;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; EXHIBITIONS; MICROPROCESSOR CHIPS;

DESIGN;

EID: 84893714498     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269205     Document Type: Conference Paper

References (6)

1. "Reduction of Interconnect Delay by Exploiting Crosstalk", Van Dijk, S.; Hely, D; ESSCIRC, Sept. 2001. Page 316.
2. "On-Chip Bus Attributes Specification Version 1", On-Chip Bus DWG (OCB 1 2.0). September 2001. VSI Alliance WEB site, http://www.vsi.org/.
3. "A structured and scalable mechanism for test access to embedded reusable cores", Marinissen, E.J.; Arendsen, R.; Bos, G.; Dingemanse, H.; Lousberg, M.; Wouters, C.; IEEE International Test Conference, 1998. Oct. 1998. Page(s): 284-293.
4. IEEE P1500 WEB site, http://grouper.ieee.org/groups/1500.
5. Collett Research International Inc., Cupertino, CA.
6. "Core-Based Scan Architecture for Silicon Debug", Vermeulen, B.; Waayers, T.; Goel, S.K.; IEEE International Test Conference, 2002. Oct. 2002. Page (s): 638-647.