Automatic memory partitioning: Increasing memory parallelism via data structure partitioning

Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010

Volumn , Issue , 2010, Pages 155-161

  Asher, Yosi Ben ^a   Rotem, Nadav ^a  

^a UNIVERSITY OF HAIFA   (Israel)

Author keywords

FPGA; Memory; Parallelism

Indexed keywords

FPGA; HIGH LEVEL SYNTHESIS; MEMORY; MEMORY ACCESS PATTERNS; MEMORY BANKS; MEMORY REGION; MEMORY TRACES; PARALLEL MEMORY; PARALLELISM; SOURCE CODE INSTRUMENTATION;

COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING; DATA HANDLING; DATA STRUCTURES;

EMBEDDED SYSTEMS; DATA HANDLING;

EID: 78650671133     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1878961.1878989     Document Type: Conference Paper

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