Memory Allocation and Mapping in High-Level Synthesis - An Integrated Approach

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 5, 2003, Pages 928-938

  Seo, Jaewon ^a   Kim, Taewhan ^a   Panda, Preeti Ranjan ^b  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

High level synthesis; Memory allocation; Memory mapping

Indexed keywords

ALGORITHMS; ARRAYS; BEHAVIORAL RESEARCH; DATA REDUCTION;

MEMORY MAPPING;

STORAGE ALLOCATION (COMPUTER);

EID: 0142227160     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.817116     Document Type: Article

References (14)

1. W.-T. Shiue, S. Tadas, and C. Chakrabarti, "Low power multi-module, multi-port memory design for embedded systems," in Proc. Signal Processing Systems, 2000, pp. 529-538.
2. N. Holmes and D. Gajski, "Architectural exploration for datapaths with memory hierarchy," in Proc. European Design Automation Conf., 1994, pp. 340-344.
3. L. Ramachandran, D. Gajski, and V. Chaiyakul, "An algorithm for array variable clustering," in Proc. European Design Automation Conf., 1994, pp. 262-266.
4. P. R. Panda, "Memory bank customization and assignment in behavioral synthesis," in Proc. Int. Conf. Computer-Aided Design, 1999, pp. 477-481.
5. P. R. Panda, N. Dutt, and A. Nicolau, "Incorporating DRAM access modes into high-level synthesis," IEEE Trans. Computer-Aided Design, vol. 17, pp. 96-109, Feb. 1998.
6. S. Wuytack, F. Catthoor, D. De Jong, and H. De Man, "Minimizing the required memory bandwidth in VLSI system realizations," IEEE Trans. VLSI Syst., vol. 7, pp. 433-441, 1999.
7. P. R. Panda, F. Catthoor, N. Dutt, K. Danckaert, E. Brockmeyer, C. Kulkarni, A. Vandercappelle, and P. G. Kjeldsberg, "Data and memory optimization techniques for embedded systems," ACM Trans. Design Automation Electron. Syst., vol. 6, no. 2, pp. 149-206, Apr. 2001.
8. J. M. Mulder, N. T. Quach, and M. J. Flynn, "An area model for on-chip memories and its application," IEEE J. Solid-State Circuits, vol. 26, pp. 98-105, Feb. 1991.
9. D. Lanneer, M. Cornero, G. Goosesens, and H. De Man, "Data routing: A paradigm for efficient data-path synthesis and code generation," in Proc. Int. Symp. High-level Synthesis, 1994, pp. 17-22.
10. P. G. Paulin and J. P. Knight, "Force-directed scheduling for the behavioral synthesis of ASIC's," IEEE Trans. Computer-Aided Design, vol. 8, pp. 661-679, 1989.
11. P. R. Panda and N. D. Dutt, "1995 high-level synthesis design repository," in Proc. Int. Symp. System Synthesis, 1995, pp. 170-174.
12. H. Schmit and D. E. Thomas, "Synthesis of application-specific memory designs," IEEE Trans. VLSI Syst., vol. 5, pp. 101-111, Mar. 1997.
13. W. H. Press, B. P. Flannery, S. A. Teukolsky, and W. T. Vetterling, Numerical Recipes in C, Cambridge, U.K.: Cambridge Univ. Press, 1988.
14. C. Lee, M. Potkonjak, and W. H. Mangione-Smith, "Mediabench: A tool for evaluating and synthesizing multimedia and communication systems," IEEE/ACM Int. Symp. Microarchitecture, pp. 330-335, 1997.