Automatic on-chip memory minimization for data reuse

Proceedings 2007 IEEE Symposium on Field-Programme Custom Computing Machines, FCCM 2007

Volumn , Issue , 2007, Pages 251-260

  Liu, Qiang ^a   Constantinides, George A ^a   Masselos, Konstantinos ^b   Cheung, Peter Y K ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

^b UNIVERSITY OF PELOPONNESE   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

ADDRESS MAPPINGS; CLOCK PERIOD; FPGA-BASED COMPUTING; HIGH FLEXIBILITY; MEMORY ACCESS PATTERNS; OFF-CHIP COMMUNICATION; ON CHIP MEMORY; ON-CHIP STORAGE;

RANDOM ACCESS STORAGE;

EID: 47349118796     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2007.18     Document Type: Conference Paper

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