A 40 nm LP CMOS PLL for high-speed mm-wave communication

ESSCIRC 2010 - 36th European Solid State Circuits Conference

Volumn , Issue , 2010, Pages 254-257

  Parvais, B ^a   Scheir, K ^a   Vidojkovic, V ^a   Vandebriel, R ^a   Vandersteen, G ^b   Soens, C ^a   Wambacq, P ^a,b  

^a IMEC   (Belgium)

^b VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; HIGH-SPEED; IN-BAND PHASE NOISE; INJECTION LOCKED; INTEGER-N; MM-WAVE; PRESCALERS; RADIO ARCHITECTURES; TYPE II; ZERO IF;

CMOS INTEGRATED CIRCUITS; FREQUENCY BANDS; PHASE LOCKED LOOPS;

PHASE NOISE;

EID: 78650317016     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2010.5619881     Document Type: Conference Paper

References (14)

1. IEEE 802.15 WPAN Millimeter wave alternative PHY task group 3c (TG3c) http://www.ieee802.org/15/pub/TG3c.html.
2. Standard ECMA-387 for High Rate 60 GHz PHY, MAC , HDMI PAL, http://www.ecma-international.org/publications/standards/Ecma-387.htm.
3. O. Richard et al., "A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for Wireless HD Applications," Proceedings of ISSCC, pp. 252-254, February 2010.
4. K. Scheir, G. Vandersteen, Y. Rolain and P. Wambacq, "A 57-to- 66GHz Quadrature PLL in 45nm Digital CMOS," Proceedings of ISSCC, pp. 493-495, February 2009.
5. C. Charles and D. Allstot, "A Calibrated Phase/Frequency Detector for Reference Spur Reduction in Charge-Pump PLLs," IEEE Trans. CAS II, Vol. 43, No. 9, pp. 822-826, Sept. 2006.
6. P. Andreani, A. Bonfanti, L. Romano and C. Samori, "Analysis and Design of a 1.8-GHz CMOS LC Quadrature VCO", IEEE J. Solid-State Circuits, Vol. 37, no. 12, pp. 1737-1747, December 2002.
7. A. Mirzaei, "The Quadrature LC Oscillator: A Complete Portrait Based on Injection Locking," IEEE J. Solid-State Circuits, vol. 42, pp. 1916-1932, Sept. 2007.
8. S. Gierkink, S. Levantino, R. Frye and V. Boccuzzi, "A Low Phase noise 5GHz Quadrature CMOS VCO using Common-Mode Inductive Coupling," Proceedings of ESSCIRC, pp. 539-542, September 2002.
9. J. Borremans, K. Raczkowski and P. Wambacq, "A digitally-controlled compact 57-66GHz receiver front-end for phased-arrays in 45nm digital CMOS", Proceedings of ISSCC, pp. 492-493, February 2009.
10. K.-H. Tsai, J.-H. Wu and S.-I. Liu, "A digitally calibrated 64.3- 66.2GHz phased-locked loop", Proceedings of RFIC, pp. 307-310, May 2008.
11. H. Hoshino, R. Tachibana, T. Mitomo, N. Ono, Y. Yoshihara and R. Fujimoto, "A 60GHz phased-locked loop with inductorless prescaler in 90nm CMOS", Proceedings of ESSCIRC, pp. 427-475, September 2007.
12. C. Lee and S. Luan Liu, "A 58-60.4GHz frequency synthesizer in 90nm CMOS", Proceedings of ISSCC, pp. 196-596, February 2007.
13. Z. Xu, Q. J. Gu, Y.-C. Wu, H.-Y. Jian, F. Wang, M.-C. F. Chang, "An integrated frequency synthesizer for 81-86 satellite communications in 65nm CMOS, Proceedings of RFIC, pp. 57-60, May 2010.
14. K.H. Tsai, S.I. Liu, "A 43.7mW 96GHz PLL in 65nm CMOS" Proceedings of ISSCC, pp. 276-277, February 2009.