A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 252-253

  Richard, Olivier ^a   Siligaris, Alexandre ^b   Badets, Franck ^a   Dehos, Cedric ^b   Dufis, Cedric ^a   Busson, Pierre ^a   Vincent, Pierre ^b   Belot, Didier ^a   Urard, Pascal ^a  

^a STMICROELECTRONICS   (France)

^b CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

65NM CMOS TECHNOLOGY; DOUBLE CONVERSION; FOUR-CHANNEL; FREQUENCY SYNTHESIS; FREQUENCY TUNING RANGE; IEEE 802.15.3C; KEY ELEMENTS; LARGE BAND; LOCAL OSCILLATORS; LOW PHASE NOISE; MM-WAVE BAND; OUTPUT BUFFER; PHASE NOISE PERFORMANCE; SUPER-HETERODYNE ARCHITECTURE; TOTAL POWER DISSIPATION; TRADE OFF; TUNING RANGES; WIDE TUNING RANGE;

CMOS INTEGRATED CIRCUITS; COMMUNICATION SYSTEMS; FREQUENCY SYNTHESIZERS; PACKET NETWORKS; PHASE NOISE; SYNTHESIS (CHEMICAL); TRANSCEIVERS; TUNING;

PHASE LOCKED LOOPS;

EID: 77952202327     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433941     Document Type: Conference Paper

References (5)

1. S. Pellerano, R. Mukhopadhyay, A. Ravi, L. Laskar, Y. Palaskas, "A 39.1-to-41.6GHz ΔΣ Fractional-N Frequency Synthesizer in 90nm CMOS", ISSCC Dig. Tech. Papers, pp.484-485, 3-7 Feb. 2008.
2. K. Scheir, G. Vandersteen, Y. Rolain, P. Wambacq, "A 57-to-66GHz Quadrature PLL in 45nm Digital CMOS", ISSCC Dig. Tech. Papers, pp.494-495, 8-12 Feb. 2009.
3. C. Lee, S. Liu, "A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS", ISSCC Dig. Tech. Papers, pp.196-197, 11-15 Feb. 2007.
4. K. Tsai, S. Liu, "A 43.7mW 96GHz PLL in 65nm CMOS", ISSCC Dig. Tech. Papers, pp.276-277, 8-12 Feb. 2009.
5. B. Razavi, K.-F. Lee, R.-H. Yan, "A 13.4GHz CMOS Frequency Divider", ISSCC, pp.176-177, 1994.