A digitally calibrated 64.3-66.2GHz phase-locked loop

Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

Volumn , Issue , 2008, Pages 307-310

  Tsai, Kun Hung ^a   Wu, Jia Hao ^a   Liu, Shen Iuan ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Clock generator; CMOS; Digital calibration; Frequency divider; Phase locked loop

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; ELECTRONICS INDUSTRY; NETWORKS (CIRCUITS); PHASE LOCKED LOOPS; RADIO WAVES; SPURIOUS SIGNAL NOISE; TELECOMMUNICATION;

CLOCK GENERATOR; CMOS; CMOS TECHNOLOGIES; DIGITAL CALIBRATION; DIGITAL CALIBRATIONS; FREQUENCY DIVIDER; OPERATION FREQUENCIES; OUTPUT BUFFERS; PHASE-LOCKED LOOP; PHASE-NOISE; RADIO FREQUENCY INTEGRATED CIRCUITS;

INTEGRATED CIRCUITS;

EID: 52149112062     PISSN: 15292517     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RFIC.2008.4561442     Document Type: Conference Paper

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