A 57-to-66GHz quadrature PLL in 45nm digital CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 494-496

  Scheir, K ^a,b   Vandersteen, G ^b   Rolain, Y ^b   Wambacq, P ^a,b  

^a IMEC   (Belgium)

^b VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349297486     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977524     Document Type: Conference Paper

References (6)

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2. K.-H. Tsai, J.-H. Wu and S.-I. Liu, "A Digitally Calibrated 64.3-to-66.2GHz Phase- Locked Loop", IEEE Radio Frequency Integrated Circuits Symp., pp. 307-310, 2008.
3. H. Hoshino, R. Tachibana, T. Mitomo, N. Ono, Y. Yoshihara and R. Fujimoto, "A 60GHz Phase-Locked Loop with Inductorless Prescaler in 90nm CMOS", European Solid-State Circuits Conf., pp. 427-475, 2007.
4. C. Lee and S. Luan Liu, "A 58-60.4GHz Frequency Synthesizer in 90nm CMOS", ISSCC Dig. Tech. Papers, pp. 196-197, 2007.
5. C. Cao, Y. Ding and K. O, "A 50GHz Phase-Locked Loop in 0.13μm CMOS", IEEE J. Solid-State Circuits, vol.42, no.8, pp. 1649-1656, Aug. 2007.
6. C. S. Vaucher, I. Ferencic, M. Locker, S. Sedvallson, U. Voegeli and Z. Wang, "A Family of Low-Power Truly-Modular Programmable Dividers in Standard 0.35μm CMOS Technology", IEEE J. Solid-State Circuits, vol.39, no.5, pp. 775-784, May 2004.