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Volumn , Issue , 2009, Pages

A 43.7mW 96GHz PLL in 65nm CMOS

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EID: 70349389669     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977415     Document Type: Conference Paper
Times cited : (61)

References (9)
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    • C. Cao, Y. Ding, and K.K. O, "A 50-GHz Phase-Locked Loop in 0.13-μm CMOS," IEEE J. Solid-State Circuits, vol.42, no.8, pp. 1649-1656, Aug., 2007.
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  • 4
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    • J. Lee, M. Liu, and H. Wang, "A 75-GHz Phase-Locked Loop Generator in 90-nm CMOS Technology," IEEE J. Solid-State Circuits, vol.43, no.6, pp. 1414-1426, Jun., 2008.
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    • B. Heydari, M. Bohsali, E. Adabi, and A.M. Niknejad, "Millimeter- Wave Devices and Circuit Blocks up to 104 GHz in 90 nm CMOS," IEEE J. Solid-State Circuits, vol.42, no.12, pp. 2893-2903, Dec., 2007.
    • (2007) IEEE J. Solid-State Circuits , vol.42 , Issue.12 , pp. 2893-2903
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  • 7
    • 34548853685 scopus 로고    scopus 로고
    • A 58-to-60.4GHz frequency synthesizer in 90nm CMOS
    • Feb.
    • C. Lee and S.-I. Liu, "A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 196-197, Feb., 2007.
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    • Lee, C.1    Liu, S.-I.2
  • 8
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.