Achieving fair or differentiated cache sharing in power-constrained chip multiprocessors

Proceedings of the International Conference on Parallel Processing

Volumn , Issue , 2010, Pages 1-10

  Wang, Xiaorui ^a   Ma, Kai ^a   Wang, Yefu ^a  

^a University of Tennessee   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION THREADS; CACHE ACCESS; CACHE LATENCY; CACHE MANAGEMENT; CACHE SHARING; CHIP MULTIPROCESSOR; CHIP-LEVEL POWER; CONTROL ARCHITECTURE; DYNAMIC CACHE; L2 CACHE; LOW-POWER MODE; ON-CHIP L2 CACHE; PEAK POWER; PERFORMANCE TRADE-OFF; POWER CAPPING;

CACHE MEMORY; MULTIPROCESSING SYSTEMS; SYSTEM STABILITY;

CONTROL SYSTEM STABILITY;

EID: 78649603166     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2010.9     Document Type: Conference Paper

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