Accelerating multicore reuse distance analysis with sampling and parallelization

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2010, Pages 53-63

  Schuff, Derek L ^a   Kulkarni, Milind ^a   Pai, Vijay S ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

multicore performance analysis; parallel performance analysis; performance analysis; reuse distance

Indexed keywords

COMPUTER SOFTWARE REUSABILITY; MULTITASKING; PARALLEL ARCHITECTURES; PROGRAM COMPILERS;

COMPILER OPTIMIZATIONS; MEASUREMENT METHODS; MULTI-THREADED PROGRAMS; NEW MEASUREMENT METHOD; PARALLEL PERFORMANCE ANALYSIS; PERFORMANCE ANALYSIS; PERFORMANCE PENALTIES; REUSE DISTANCE;

BENCHMARKING;

EID: 78149254514     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1854273.1854286     Document Type: Conference Paper

References (40)

1. G. Almási, C. Caşcaval, and D. A. Padua. Calculating stack distances efficiently. SIGPLAN Not., 38(2 supplement):37-43, 2003.
2. V. Aslot, R. Eigenmann, G. Gaertner, W. B. Jones, and B. Parady. Specomp: A new benchmark suite for measuring parallel computer performance. In Workshop on OpenMP Applications and Tools, pages 1-10, 2001.
3. B. T. Bennett and V. J. Kruskal. Lru stack processing. IBM Journal of Research and Development, 19:353-357, 1975.
4. E. Berg and E. Hagersten. Statcache: a probabilistic approach to efficient and accurate data locality analysis. In Proc. of 2004 IEEE ISPASS, pages 20-27, 2004.
5. E. Berg and E. Hagersten. Fast data-locality profiling of native execution. In Proc. of SIGMETRICS '05, pages 169-180, New York, NY, USA, 2005. ACM.
6. E. Berg, H. Zeffer, and E. Hagersten. A statistical multiprocessor cache model. Proc. of 2006 IEEE ISPASS, pages 89-99, March 2006.
7. K. Beyls and E. D'Hollander. Reuse distance as a metric for cache behavior. In Proc. of IASTED Conference on Parallel and Distributed Computing and Systems, pages 617-662, 2001.
8. K. Beyls and E. D'Hollander. Platform-independent cache optimization by pinpointing low-locality reuse. In Proc. 4th Intl. Conf. on Computational Science, volume 3038, pages 448-455, 6 2004.
9. K. Beyls and E. D'Hollander. Generating cache hints for improved program efficiency. Journal of Systems Architecture, 51(4):223-250, 4 2005.
10. K. Beyls and E. D'Hollander. Discovery of locality-improving refactorings by reuse path analysis. In Proc. 2nd Intl. Conf. on High Performance Computing and Communications (HPCC), 2006.
11. K. Beyls, E. D'Hollander, and F. Vandeputte. Rdvis: A tool that visualizes the causes of low locality and hints program optimizations. In Proc. 5th Intl. Conf. on Computational Science, 2005.
12. C. Bienia, S. Kumar, J. P. Singh, and K. Li. The parsec benchmark suite: characterization and architectural implications. In Proc. of PACT '08, pages 72-81, New York, NY, USA, 2008. ACM.
13. C. Cao Minh, J. Chung, C. Kozyrakis, and K. Olukotun. STAMP: Stanford transactional applications for multi-processing. In Proc. of The IEEE International Symposium on Workload Characterization, 2008.
14. D. Chandra, F. Guo, S. Kim, and Y. Solihin. Predicting inter-thread cache contention on a chip multi-processor architecture. In Proc. of HPCA '05, pages 340-351, Washington, DC, USA, 2005. IEEE Computer Society.
15. D. Dice, O. Shalev, and N. Shavit. Transactional Locking II. In Proc. of 20th Intl. Symp. on Distributed Computing, pages 194-208, 2006.
16. C. Ding and T. Chilimbi. A composable model for analyzing locality of multi-threaded programs. Technical Report MSR-TR-2009-107, Microsoft Research, 2009.
17. C. Ding and Y. Zhong. Predicting whole-program locality through reuse distance analysis. In Proc. of ACM SIGPLAN PLDI '03, 2003.
18. D. Eklov and E. Hagersten. Statstack: Efficient modeling of lru caches. In Proc. of 2010 IEEE ISPASS, pages 55-65, 28-30 2010.
19. C. Fang, S. Carr, S. Önder, and Z. Wang. Reuse-distance-based miss-rate prediction on a per instruction basis. In Proc. of 1st Workshop on Memory System Performance, 2004.
20. Y. Jiang, E. Zhang, and K. Tian. Is reuse distance applicable to data locality analysis on chip multiprocessors. In Proc. of Intl. Conf. on Compiler Construction, Paphos, Cyprus, March 2010.
21. H. Jin, M. Frumkin, and J. Yan. The OpenMP implementation of NAS parallel benchmarks and its performance.
22. S. Kim, D. Chandra, and Y. Solihin. Fair cache sharing and partitioning in a chip multiprocessor architecture. In Proc. of PACT '04, pages 111-122, Washington, DC, USA, 2004. IEEE Computer Society.
23. E. Larson and S. Chatterjee. Mase: A novel infrastructure for detailed microarchitectural modeling. In Proc. of 2001 IEEE ISPASS, 2001.
24. C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood. Pin: building customized program analysis tools with dynamic instrumentation. In Proc. of ACM SIGPLAN PLDI '05, 2005.
25. G. Marin and J. Mellor-Crummey. Cross-architecture performance predictions for scientific applications using parameterized models. In Proc. of SIGMETRICS '04/Performance '04, pages 2-13, New York, NY, USA, 2004. ACM.
26. G. Marin and J. Mellor-Crummey. Pinpointing and exploiting opportunities for enhancing data reuse. In Proc. of 2008 IEEE ISPASS, 2008.
27. R. L. Mattson, J. Gecsei, D. R. Slutz, and I. L. Traiger. Evaluation Techniques for Storage Hierarchies. IBM Systems Journal, 9(2):78-117, 1970.
28. N. Nethercote and J. Seward. Valgrind: a framework for heavyweight dynamic binary instrumentation. In Proc. of ACM SIGPLAN PLDI '07, pages 89-100, New York, NY, USA, 2007. ACM.
29. NIST/SEMATECH. e-Handbook of Statistical Methods, June 2003.
30. F. Olken. Efficient methods for calculating the success function of fixed space replacement policies. Technical Report LBL-12370, Lawrence Berkeley Laboratory, 1981.
31. D. L. Schuff, B. S. Parsons, and V. S. Pai. Multicore-aware reuse distance analysis. Technical Report TR-ECE-09-08, Purdue University, 2009.
32. D. L. Schuff, B. S. Parsons, and V. S. Pai. Multicore-aware reuse distance analysis. In Workshop on Performance Modeling, Evaluation, and Optimisation of Ubiquitous Computing and Networked Systems, 2010.
33. J. Seward and N. Nethercote. Using Valgrind to detect undefined value errors with bit-precision. In Proc. of 2005 Usenix Annual Technical Conference, Apr. 2005.
34. X. Shen, Y. Zhong, and C. Ding. Locality phase prediction. In Proc. of ASPLOS-XI, 2004.
35. X. Shi, F. Su, J.-K. Peir, Y. Xia, and Z. Yang. Modeling and single-pass simulation of cmp cache capacity and accessibility. In Proc. of 2007 IEEE ISPASS, pages 126-135, 2007.
36. R. A. Sugumar and S. G. Abraham. Multi-configuration simulation algorithms for the evaluation of computer architecture designs. Technical report, University of Michigan, 1993.
37. G. E. Suh, S. Devadas, and L. Rudolph. Analytical cache models with applications to cache partitioning. In Proc. of 15th Intl. Conf. on Supercomputing, 2001.
38. D. W. Wall. Predicting program behavior using real or estimated profiles. SIGPLAN Not., 39(4):429-441, 2004.
39. Y. Zhong and W. Chang. Sampling-based program locality approximation. In Proc. of 7th Intl. Symp. on Memory Management, pages 91-100, New York, NY, USA, 2008. ACM.
40. Y. Zhong, S. G. Dropsho, and C. Ding. Miss rate prediction across all program inputs. In In Proc. of PACT '03, 2003.