StatStack: Efficient modeling of LRU caches

ISPASS 2010 - IEEE International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2010, Pages 55-65

  Eklov, David ^a   Hagersten, Erik ^a  

^a UPPSALA UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK SUITES; DATA COLLECTION; DATA OBJECTS; DISTANCE-BASED; GOOD DATA; HARDWARE COUNTERS; MEMORY ACCESS; MISS-RATE; MODERN ARCHITECTURES; OFF-LINE ALGORITHM;

ABSTRACTING; BENCHMARKING; COMPUTER SOFTWARE;

ESTIMATION;

EID: 77952570425     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2010.5452069     Document Type: Conference Paper

References (27)

1. B. T. Bennett and V. J. Kruskal. LRU Stack Processing. IBM Journal of Research and Development, pages 353-357, 1975.
2. E. Berg and E. Hagersten. StatCache: A Probabilistic Approach to Efficient and Accurate Data Locality Analysis. In Proceedings of the 2004 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2004), Austin, Texas, USA, Mar. 2004.
3. E. Berg and E. Hagersten. Fast Data-Locality Profiling of Native Execution. In Proceedings of ACM SIGMETRICS 2005, Banff, Canada, June 2005.
4. E. Berg, H. Zeffer, and E. Hagersten. A Statistical Multiprocessor Cache Model. In Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2006), Austin, Texas, USA, Mar. 2006.
5. K. Beyls and E. H. D'Hollander. Generating Cache Hints for Improved Program Efficiency. J. Syst. Archit., 51(4):223-250, 2005.
6. D. Chandra, F. Guo, S. Kim, and Y. Solihin. Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture. In Proceedings of the 11th International Symposium on High-Performance Computer Architecture, pages 340-351. IEEE Computer Society, 2005.
7. A. S. Dhodapkar and J. E. Smith. Comparing Program Phase Detection Techniques. In MICRO 36: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, page 217, Washington, DC, USA, 2003. IEEE Computer Society.
8. C. Ding and M. Orlovich. The Potential of Computation Regrouping for Improving Locality. In Proceedings of the 2004 ACM/IEEE conference on Supercomputing, page 13. IEEE Computer Society, 2004.
9. C. Ding and Y. Zhong. Predicting Whole-Program Locality Through Reuse Distance Analysis. SIGPLAN Not., 38(5):245-257, 2003.
10. L. Eeckhout, S. Niar, and K. D. Bosschere. Optimal Sample Length for Efficient Cache Simulation. J. Syst. Archit., 51(9):513-525, 2005.
11. D. Eklov and E. Hagersten. Statstack: Efficient Modeling of LRU Caches. Technical Report 2009-019, Department of Information Technology, Uppsala University, July 2009.
12. L. V. Ertvelde, F. Hellebaut, L. Eeckhout, and K. D. Bosschere. NSL-BLRL: Efficient Cache Warmup for Sampled Processor Simulation. In ANSS '06: Proceedings of the 39th annual Symposium on Simulation, pages 168-177, Washington, DC, USA, 2006. IEEE Computer Society.
13. R. E. Kessler, M. D. Hill, and D. A. Wood. A Comparison of Trace-Sampling Techniques for Multi-Megabyte Caches. IEEE Trans. Comput., 43(6):664-675, 1994.
14. C. keung Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. Janapa, and R. K. Hazelwood. Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation. In In Programming Language Design and Implementation, pages 190-200. ACM Press, 2005.
15. Y. H. Kim, M. D. Hill, and D. A. Wood. Implementing Stack Simulation for Highly-Associative Memories. SIGMETRICS Perform. Eval. Rev., 19(1):212-213, 1991.
16. S. Laha, J. H. Patel, and R. K. Iyer. Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems. IEEE Trans. Comput., 37(11):1325-1336, 1988.
17. R. L. Mattson, J. Gecsei, D. R. Slutz, and I. L. Traiger. Evaluation Techniques for Storage Hierarchies. IBM Systems Journal, 9(2):78-117, 1970.
18. N. Nethercote and J. Seward. Valgrind: A Framework for Heavyweight Dynamic Binary Instrumentation. SIGPLAN Not., 42(6):89-100, 2007.
19. F. Olken. Efficient Methods for Calculating the Success Function of Fixed Space Replacement Policies. Technical report, Lawrence Berkeley Lab, Aug. 1993.
20. B. M. Rogers, A. Krishna, G. B. Bell, K. Vu, X. Jiang, and Y. Solihin. Scaling the Bandwidth Wall: Challenges in and Avenues for CMP Scaling. SIGARCH Comput. Archit. News, 37(3):371-382, 2009.
21. X. Shen, J. Shaw, B. Meeker, and C. Ding. Locality Approximation Using Time. SIGPLAN Not., 42(1):55-61, 2007.
22. X. Shen, Y. Zhong, and C. Ding. Locality Phase Prediction. In Proceedings of the 11th international conference on Architectural support for programming languages and operating systems, pages 165-176, Boston, MA, USA, 2004. ACM.
23. T. Sherwood, E. Perelman, G. Hamerly, S. Sair, and B. Calder. Discovering and Exploiting Program Phases. IEEE Micro, 23(6):84-93, 2003.
24. R. A. Sugumar and S. G. Abraham. Efficient Simulation of Caches Under Optimal Replacement with Applications to Miss Characterization. In Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and modeling of computer systems, pages 24-35, Santa Clara, California, United States, 1993. ACM.
25. D. K. Tam, R. Azimi, L. B. Soares, and M. Stumm. RapidMRC: Approximating L2 Miss Rate Curves on Commodity Systems for Online Optimizations. In ASPLOS '09: Proceeding of the 14th international conference on Architectural support for programming languages and operating systems, pages 121-132, New York, NY, USA, 2009. ACM.
26. R. E. Wunderlich, T. F. Wenisch, B. Falsafi, and J. C. Hoe. SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling. SIGARCH Comput. Archit. News, 31(2):84-97, 2003.
27. Y. Zhong, S. G. Dropsho, X. Shen, A. Studer, and C. Ding. Miss Rate Prediction Across Program Inputs and Cache Configurations. IEEE Transactions on Computers, 56(3):328-343, 2007.