A QoS network architecture to interconnect large-scale VLSI neural networks

Proceedings of the International Joint Conference on Neural Networks

Volumn , Issue , 2009, Pages 2525-2532

  Philipp, Stefan ^a   Schemmel, Johannes ^a   Meier, Karlheinz ^a  

^a UNIVERSITY OF HEIDELBERG   (Germany)

Author keywords

AER; Crossbar switches; Isochronous communication; Quality of service; VLSI neural networks

Indexed keywords

AER; ARTIFICIAL NEURONS; BEST-EFFORT; CIRCUIT SWITCHING; CROSSBAR SWITCHES; DATA-FORWARDING; DIFFERENT SERVICES; DISTRIBUTED ANN; END TO END DELAY; ISOCHRONOUS COMMUNICATION; ISOCHRONOUS CONNECTION; LOW COMPLEXITY; MULTI-PURPOSE; NETWORK ENVIRONMENTS; NETWORK NODE; ON-DEMAND; ORDERS OF MAGNITUDE; PACKET PROCESSING; PACKET TRANSFER; PORT NUMBERS; PROGRAMMABLE LOGIC; QOS NETWORKS; REFERENCE IMPLEMENTATION; REMAINING BANDWIDTH; SWITCH ARCHITECTURES; VLSI NEURAL NETWORKS;

BACKPROPAGATION; BIOLOGY; CROSSBAR EQUIPMENT; JITTER; NEURAL NETWORKS; PACKET SWITCHING; QUALITY CONTROL; QUALITY OF SERVICE; SWITCHES; SWITCHING CIRCUITS; SWITCHING NETWORKS; TELECOMMUNICATION SYSTEMS;

NETWORK ARCHITECTURE;

EID: 70449434376     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IJCNN.2009.5178983     Document Type: Conference Paper

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