Tri-level resistive switching in metal-nanocrystal-based Al 2O3/SiO2 gate stack

IEEE Transactions on Electron Devices

Volumn 57, Issue 11, 2010, Pages 3001-3005

  Chen, Y N ^a   Pey, K L ^a   Goh, K E J ^b   Lwin, Z Z ^a   Singh, P K ^c   Mahapatra, S ^c  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b INSTITUTE OF MATERIALS RESEARCH AND ENGINEERING   (Singapore)

^c INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

Author keywords

Dielectric breakdown; metal nanocrystal (MNC); percolation path; resistive switching

Indexed keywords

DIELECTRIC BREAKDOWNS; DIELECTRIC LAYER; ELECTRICAL METHODS; FORMING PROCESS; GATE BIAS; GATE STACKS; HIGH-RESISTANCE STATE; LOW-RESISTANCE STATE; METAL NANOCRYSTALS; METAL OXIDE INTERFACE; PERCOLATION PATH; PHYSICAL MODEL; RESISTANCE RATIO; RESISTANCE STATE; RESISTIVE SWITCHING; RESISTIVE SWITCHING BEHAVIORS; RESISTIVE SWITCHING MEMORIES; SWITCHING TRANSITIONS; TRAPPING/DETRAPPING;

ALUMINUM; ELECTRIC BREAKDOWN; LOGIC GATES; METALS; NANOCRYSTALS; OXYGEN; OXYGEN VACANCIES; SILICON COMPOUNDS; SOLVENTS; SWITCHING SYSTEMS; THERMAL NOISE;

SWITCHING;

EID: 78049273681     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2070801     Document Type: Article

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