A binary-tree hierarchical multiple-chip architecture for real-time large-scale learning processor systems

Japanese Journal of Applied Physics

Volumn 49, Issue 4 PART 2, 2010, Pages

  Ma, Yitao ^a   Shibata, Tadashi ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP ARCHITECTURE; CHIP AREAS; COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TECHNOLOGIES; COMPUTATIONAL SPEED; DATA-COMMUNICATION; DEDICATED PROCESSORS; EMBEDDED MEMORIES; HIERARCHICAL STRUCTURES; INTER-CHIP; K-MEANS CLUSTERING ALGORITHM; MASSIVELY PARALLEL PROCESSING; PROCESSOR ARCHITECTURES; PROCESSOR SYSTEMS; PROOF OF CONCEPT; REAL-TIME LEARNING; SAMPLE DATA; TEST CHIPS;

CLUSTERING ALGORITHMS; COMPUTER ARCHITECTURE; HIERARCHICAL SYSTEMS; LEARNING ALGORITHMS; NANOTECHNOLOGY; REAL TIME SYSTEMS;

TREES (MATHEMATICS);

EID: 77952730407     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.49.04DE08     Document Type: Article

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