Realization of a programmable rank-order filter architecture using capacitive threshold logic gates

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1999, Pages

  Hatirnaz, I ^a   Gurkaynak, F K ^a   Leblebici, Y ^a  

^a WORCESTER POLYTECHNIC INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; IMAGE ENHANCEMENT; IMAGE PROCESSING; LOGIC GATES;

CAPACITATIVE THRESHOLD LOGIC GATES; PROGRAMMABLE RANK ORDER FILTER;

DIGITAL FILTERS;

EID: 0032692253     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (7)