Impact of charge trapping on the voltage acceleration of TDDB in metal gate/high-k n-channel MOSFETs

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2010, Pages 369-372

  Kerber, A ^a   Vayshenker, A ^b   Lipp, D ^c   Nigam, T ^a   Cartier, E ^d  

^a IBM MICROELECTRONICS   (United States)

^b IBM RESEARCH   (United States)

^c GLOBALFOUNDRIES   (Germany)

^d IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

High k dielectrics; Metal gate; Oxygen vacancies; SILC; TDDB

Indexed keywords

AC STRESS; HIGH-K DIELECTRIC; HIGH-K GATE DIELECTRICS; METAL GATE; MOSFETS; N-CHANNEL; POWER-LAW VOLTAGE; ROOT CAUSE; SILC; STRESS CONDITION; STRESS VOLTAGES; TDDB; VOLTAGE ACCELERATION;

CHARGE TRAPPING; DC POWER TRANSMISSION; DIELECTRIC MATERIALS; GATES (TRANSISTOR); METALS; OXYGEN; OXYGEN VACANCIES;

GATE DIELECTRICS;

EID: 77957917074     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2010.5488803     Document Type: Conference Paper

References (10)

1. C. Prasad, M. Agostinelli, C. Auth, M. Brazier, R. Chau, G. Dewey, T. Ghani, M. Hattendorf, J. Hicks, J. Jopling, J. Kavalieros, R. Kotlyar, M. Kuhn, K. Kuhn, J. Maiz, B. McIntyre, M. Metz, K. Mistry, S. Pae, W. Rachmady, S. Ramey, A. Roskowski, J. Sandford, C. Thomas, C. Wiegand, J. Wiedemer, "Dielectric Breakdown in a 45 nm High-K/Metal Gate Process Technology", International Reliability Physics Symposium, pp. 667-668, 2008.
2. 2 stack," International Reliability Physics Symposium, pp. 181-187, 2003.
3. 2/TiN Gate Stacks during Positive Bias Temperature Stress", International Reliability Physics Symposium. pp. 486-492, 2009.
4. A. Kerber, M. Kerber, "Fast Wafer Level Data Acquisition for Reliability Characterization of sub-100 nm CMOS Technologies", International Integrated Reliability Workshop Final Report, pp. 41-45, 2004.
5. A. Kerber, E. Cartier, B.P. Linder, S.A. Krishnan and T. Nigam, "TDDB failure distribution of metal gate/high-k CMOS devices on SOI substrates", International Reliability Physics Symposium, pp. 505-509, 2009.
6. 2/TiN Gate Stacks," IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 3175-3183, 2008.
7. 2 dual layer gate dielectrics," IEEE Electron Device Lett., vol. 24, no. 2, pp. 87-89, 2003.
8. E. Wu, A. Vayshenker, E. Nowak, J. Sune, R.-P. Vollertsen, W. Lai, D. Harmon, "Experimental evidence of TBD power-law for voltage dependence of oxide breakdown in ultrathin gate oxides", IEEE Trans. Elec. Dev., vol. 49, no. 12, pp. 2244-2253, Dec. 2002.
9. M. Kerber, R. Duschl, H. Reisinger, S. Jakschik, U. Schröder, T. Hecht, S. Kudelka, "Influence of Charge Trapping on AC Reliability of high-k dielectrics", International Reliability Physics Symposium, pp. 585-586, 2004.
10. A. Kerber, S.A. Krishnan and E.A. Cartier, "Voltage Ramp Stress for Bias Temperature Instability Testing of Metal Gate/High-k Stacks", IEEE Electron Device Letters, vol. 30, no. 12, pp. 1347-1349, 2009.