Reliability for manufacturing on 45nm logic technology with high-k + metal gate transistors and Pb-free packaging

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2009, Pages 350-354

  Kasim, Rahim ^a   Connor, Chris ^a   Hicks, Jeff ^a   Jopling, Jason ^a   Litteken, Chris ^a  

^a INTEL CORPORATION   (United States)

Author keywords

45nm technology; Front end reliability; Package reliability; Process reliability; Product reliability; Yield

Indexed keywords

45NM TECHNOLOGY; FRONT END RELIABILITY; PACKAGE RELIABILITY; PROCESS RELIABILITY; PRODUCT RELIABILITY; YIELD;

DEFECT DENSITY; DEFECTS; LEAD; MANUFACTURE; MECHANICAL STABILITY; NANOTECHNOLOGY; TECHNOLOGY; TRANSISTORS;

RELIABILITY;

EID: 70449372613     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2009.5173277     Document Type: Conference Paper

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