Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 9, 2010, Pages 1301-1309

  Ghosh, Swaroop ^b   Mohapatra, Debabrata ^a   Karakonstantis, Georgios ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Adders; arithmetic logic unit; high speed design; low power; multipliers; process variation tolerant design; supply voltage scaling

Indexed keywords

ARITHMETIC LOGIC UNIT; HIGH SPEED DESIGNS; LOW POWER; MULTIPLIERS; PROCESS VARIATION; SUPPLY-VOLTAGE SCALING;

ADDERS; ASYNCHRONOUS SEQUENTIAL LOGIC; CLOCKS; OPTIMIZATION; SPEED;

DESIGN;

EID: 77956230601     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2022531     Document Type: Article

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