Low power adder with adaptive supply voltage

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2003, Pages 103-106

  Suzuki, Hiroaki ^a   Jeong, Woopyo ^a   Roy, Kaushik ^a  

^a Purdue University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY UTILIZATION; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; VLSI CIRCUITS;

POWER CONSUMPTION; RIPPLE CARRY ADDER;

ADDERS;

EID: 0344551118     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. T. Kuroda et al, "Variable Supply-Voltage Scheme for Low-Power High-Speed CMOS Digital Design," IEEE JSSC, vol. 3, pp. 454-462, Mar. 1998.
2. J. Kao et al, "A 175-mW Multiply-Accumulate Unit Using an Adaptive Supply Voltage and Body Bias Architecture," IEEE JSSC, vol. 37, pp. 1545-1554, Nov. 2002.
3. T. Kuroda et al, "A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme," IEEE JSSC, vol 31, pp. 1770-1779, Nov. 1996.
4. H. Makino et al, "An Auto-Backgate-Controlled MT-CMOS Circuit," Symp. on VLSI Circuits 1998, pp.42-43.
5. A. Chandrakasan et al, "Low-power CMOS digital design," IEEE JSSC, vol. 27, pip. 473-484, Apr. 1992.
6. N. Weste, K. Eshraghian, Principle of CMOS VLSI Design - A System Perspective, Addison-Wesley Pub Co., Oct. 1994.