Novel E-Mode GaN-on-Si MOSHEMT using a selective thermal oxidation

IEEE Electron Device Letters

Volumn 31, Issue 9, 2010, Pages 948-950

  Medjdoub, F ^a   Van Hove, M ^a   Cheng, K ^a   Marcon, D ^a   Leys, M ^a   Decoutere, S ^a  

^a IMEC   (Belgium)

Author keywords

AIN GaN MOSHEMT; GaN on Si substrate; normally off; thermal oxidation

Indexed keywords

CAP LAYERS; CONTROL SAMPLES; DRAIN LEAKAGE CURRENT; FOUR-ORDER; HIGH POWER APPLICATIONS; HIGH QUALITY; METAL-OXIDE-SEMICONDUCTOR HIGH ELECTRON MOBILITY TRANSISTOR; MOSHEMT; NORMALLY-OFF; POSITIVE VALUE; SELF-ALIGNED; SI SUBSTRATES; THERMAL OXIDATION;

DRAIN CURRENT; ELECTRON GAS; ELECTRON MOBILITY; GALLIUM ALLOYS; GALLIUM NITRIDE; HIGH ELECTRON MOBILITY TRANSISTORS; LEAKAGE CURRENTS; OXIDATION; OXYGEN; SILICON NITRIDE; SILICON WAFERS; SUBSTRATES; TRANSMISSION ELECTRON MICROSCOPY; X RAY PHOTOELECTRON SPECTROSCOPY;

SEMICONDUCTING SILICON;

EID: 77956180111     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2010.2052014     Document Type: Article

References (14)

1. Y.-F. Wu, M. Moore, A. Saxler, T. Wisleder, and P. Parikh, "40-W/mm double field-plated GaN HEMTs," in Proc. 64th Device Res. Conf., 2006, pp. 151-152.
2. F. Medjdoub, J.-F. Carlin, M. Gonschorek, E. Feltin, M. A. Py, D. Ducatteau, C. Gaquiere, N. Grandjean, and E. Kohn, "Can InAIN/GaN be an alternative to high power/high temperature AlGaN/GaN devices?" in Proc. IEDM Tech. Dig., 2006, pp. 927-930.
3. M. Higashiwaki, T. Mimura, and T. Matsui, "Enhancement-mode AIN/GaN HFETs using Cat-CVD SiN," IEEE Trans. Electron Devices, vol.54, no.6, pp. 1566-1569, Jun. 2007.
4. W. Saito, Y. Takada, M. Kuraguchi, K. Tsuda, I. Omura, T. Ogura, and H. Ohashi, "High breakdown voltage AlGaN-GaN power HEMT design and high current density switching behavior," IEEE Trans. Electron Devices, vol.50, no.12, pp. 2528-2531, Dec. 2003.
5. D. Visalli, M. Van Hove, J. Derluyn, S. Degroote, M. Leys, K. Cheng, M. Germain, and G. Borghs, "AlGaN/GaN/AlGaN double heterostruc-tures on silicon substrates for high breakdown voltage field-effect transistors with low on-resistance," Jpn. J. Appl. Phys., vol.48, p. 04C101, 2009.
6. 4 cap layer," in Proc. IEEE Int. Rel. Phys. Symp., 2010.
7. Y. Uemoto, M. Hikita, H. Ueno, H. Matsuo, H. Ishida, M. Yanagihara, T. Ueda, T. Tanaka, and D. Ueda, "Gate injection transistor (GIT)\A normally-off AlGaN/GaN power transistor using conductivity modulation," IEEE Trans. Electron Devices, vol.54, no.12, pp. 3393-3399, 2007.
8. N. Ikeda, Y. Niiyama, H. Kambayashi, Y. Sato, T. Nomura, S. Kato, and S. Yoshida, "GaN power transistors on Si substrates for switching applications," Proc. IEEE, vol.98, no.6, pp. 1-11, Jun. 2010.
9. F. Medjdoub, M. Alomari, J.-F. Carlin, M. Gonschorek, E. Feltin, M. A. Py, N. Grandjean, and E. Kohn, "Barrier layer scaling of InAIN/GaN HEMTs," IEEE Electron Device Lett., vol.29, no.5, pp. 422-425, May 2008.
10. F. Medjdoub, J. Derluyn, K. Cheng, M. Leys, S. Degroote, D. Marcon, D. Visalli, M. Van Hove, M. Germain, and G. Borghs, "Low on resistance high breakdown normally-off AIN/GaN/AlGaN DHFET on Si substrate," IEEE Electron Device Lett., vol.31, no.2, pp. 111-113, Feb. 2010.
11. M. Alomari, F. Medjdoub, J.-F. Carlin, E. Feltin, N. Grandjean, A. Chuvilin, U. Kaiser, and E. Kohn, "InAIN/GaN MOSHEMT with self-aligned thermally generated oxide recess," IEEE Electron Device Lett., vol.30, no.11, pp. 1131-1133, Nov. 2009.
12. T. Zimmermann, D. Deen, Y. Cao, J. Simon, P. Fay, D. Jena, and H. G. Xing, "AIN/GaN insulated-gate HEMTs With 2.3 A/mm output current and 480 mS/mm transconductance," IEEE Electron Device Lett., vol.29, no.7, pp. 661-664, Jul. 2008.
13. 4 surface layer," J. Appl. Phys., vol.98, p. 054501, 2005.
14. K. R. Bray, R. L. C. Wu, J. Weimer, and S. Fries-Carr, "Aluminum oxyni-tride dielectrics for high power, wide temperature capacitor applications," in Proc. 26th Symp. for Passive Components, 2006.