Tunneling current in gate dielectric stack in sub-45 nanometer CMOS devices

Physica Status Solidi (C) Current Topics in Solid State Physics

Volumn 6, Issue 12, 2009, Pages 2750-2752

  Tyagi, Hitender Kumar ^a   Prasad, B ^b   George, P J ^c  

^a KURUKSHETRA UNIVERSITY   (India)

^b KURUKSHETRA UNIVERSITY   (India)

^c KITM Bhor Saidan   (India)

Author keywords

[No Author keywords available]

Indexed keywords

BAND OFFSETS; DIELECTRIC CONSTANTS; DIRECT TUNNELING CURRENTS; DUAL LAYER; DUAL STACK; EQUIVALENT OXIDE THICKNESS; FOUR-ORDER; GATE CURRENT; GATE DIELECTRIC STACKS; GATE-LEAKAGE CURRENT; HIGH-K DIELECTRIC; INTERFACIAL LAYER; K DIELECTRICS; MULTIPLE LAYERS; NANOMETER CMOS; SINGLE LAYER; STACK STRUCTURE; SUBSTRATE INJECTION; TUNNELING CURRENT;

BUILDING MATERIALS; ELECTRON TUNNELING; GATE DIELECTRICS; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; INSULATING MATERIALS; LEAKAGE CURRENTS; SILICON COMPOUNDS; SILICON OXIDES; TUNNELING (EXCAVATION);

DIELECTRIC MATERIALS;

EID: 77955438745     PISSN: 18626351     EISSN: 16101642     Source Type: Journal    
DOI: 10.1002/pssc.200982579     Document Type: Conference Paper

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