Scaling CMOS: Finding the gate stack with the lowest leakage current

Solid-State Electronics

Volumn 49, Issue 5, 2005, Pages 695-701

  Kauerauf, Thomas ^a,b   Govoreanu, Bogdan ^a,b   Degraeve, Robin ^a   Groeseneken, Guido ^a,b   Maes, Herman ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

Barrier height; Gate dielectric; High k; k Value; Leakage current

Indexed keywords

APPROXIMATION THEORY; CURRENT DENSITY; DIELECTRIC MATERIALS; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; HIGH TEMPERATURE EFFECTS; INTEGRAL EQUATIONS; INTERFACES (MATERIALS); LEAKAGE CURRENTS; QUANTUM THEORY; SILICON COMPOUNDS; ZIRCONIUM COMPOUNDS;

BARRIER HEIGHT; EQUIVALENT OXIDE THICKNESS (EOT); HIGH-K GATE DIELECTRICS; K-VALUE; TUNNELING CURRENTS;

CMOS INTEGRATED CIRCUITS;

EID: 14844291414     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2005.01.018     Document Type: Conference Paper

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