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Volumn , Issue , 2010, Pages 1763-1768

Room-temperature chip-stack interconnection using compliant bumps and wedge-incorporated electrodes

Author keywords

[No Author keywords available]

Indexed keywords

AMBIENT AIR; AU CONE; COMPLIANT BUMP; EDGE STRUCTURES; HIGH-DENSITY; INTER-CHIP; PRESSING LOADS; ROOM TEMPERATURE;

EID: 77955190388     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490730     Document Type: Conference Paper
Times cited : (6)

References (14)
  • 9
    • 33947407658 scopus 로고    scopus 로고
    • Three-dimensional integrated circuits and the future of system-on-chip designs
    • R. S. Patti: "Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs," Proc. of the IEEE 94 (2006) 1214.
    • (2006) Proc. of the IEEE , vol.94 , pp. 1214
    • Patti, R.S.1
  • 10
    • 21244491138 scopus 로고    scopus 로고
    • Pyramid bumpsfor fine-pitch chip-stack interconnection
    • N. Watanabe, Y. Ootani, and T. Asano: "Pyramid Bumpsfor Fine-Pitch Chip-Stack Interconnection," Jpn. J. Appl. Phys. 44 (2005) 2751.
    • (2005) Jpn. J. Appl. Phys. , vol.44 , pp. 2751
    • Watanabe, N.1    Ootani, Y.2    Asano, T.3
  • 11
    • 33845591193 scopus 로고    scopus 로고
    • Wafer-level compliant bump for three-dimensional LSI with high- density area bump connections
    • N. Watanabe, T. Kojima, and T. Asano: "Wafer-level Compliant Bump for Three-Dimensional LSI with High- Density Area Bump Connections," Int. Electron Devices Meeting Technical Digest, 2005, p. 687.
    • (2005) Int. Electron Devices Meeting Technical Digest , pp. 687
    • Watanabe, N.1    Kojima, T.2    Asano, T.3
  • 12
    • 77952721429 scopus 로고    scopus 로고
    • Room-temperature large- number inter-chip connections using mechanical caulking effect of compliant bump
    • N. Watanabe and T. Asano: "Room-Temperature Large- Number Inter-Chip Connections Using Mechanical Caulking Effect of Compliant Bump," Ext. Abstr. Int.Conf. Solid State Devices and Materials, 2009, p. 368.
    • (2009) Ext. Abstr. Int.Conf. Solid State Devices and Materials , pp. 368
    • Watanabe, N.1    Asano, T.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.