New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 1445-1448

  Takahashi, Yasuhiro ^a   Yokoyama, Michio ^a  

^a YAMAGATA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMMON SUBEXPRESSION ELIMINATION; CRITICAL PATHS; FINITE IMPULSE RESPONSE FILTER; FUNCTION BLOCK; MULTIPLIERLESS; STANDARD CMOS; VERILOG HDL; VLSI DESIGN; VLSI IMPLEMENTATION;

IMPULSE RESPONSE;

FIR FILTERS;

EID: 36949029484     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464870     Document Type: Conference Paper

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