Designing multiplier blocks with low logic depth

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2002, Pages

  Dempster, A G ^a   Dimirsoy, S S ^a   Kale, I ^a  

^a UNIVERSITY OF WESTMINSTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; GRAPH THEORY; SEMICONDUCTOR DEVICE STRUCTURES;

LOGIC DEPTH; MULTIPLIER BLOCKS; POWER CONSUMPTION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036287914     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. Transition analysis in multiplier-block based FIR filter structures
2. Primitive operator digital filters
3. Constant integer multiplication using minimum adders
4. General algorithms for reduced-adder integer multiplier design
5. Use of minimum-adder multiplier blocks in FIR digital filters
6. IIR digital filter design using minimum-adder multiplier blocks
7. The cost of limit-cycle elimination in IIR digital filters using multiplier blocks
8. Efficient interpolators and filter banks using multiplier blocks
9. Reduced complexity primitive operator FIR filters for low power dissipation
10. Algorithms for reducing logic depth in multiplier blocks
11. Multiplication by integer constants
12. High-speed binary multiplier