Parallelism-aware batch scheduling: Enabling high-performance and fair shared memory controllers

IEEE Micro

Volumn 29, Issue 1, 2009, Pages 22-32

  Mutlu, Onur ^a   Moscibroda, Thomas ^b  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b MICROSOFT RESEARCH   (United States)

Author keywords

Chip multiprocessors; DRAM; Fairness; Interference; Magnetic cores; Memory controllers; Memory level parallelism; Multicore; Parallel processing; Presses; Program processors; Quality of service; Random access memory; Throughput

Indexed keywords

CONTROLLERS; DYNAMIC RANDOM ACCESS STORAGE; MAGNETIC CIRCUITS; MAGNETIC CORES; MAGNETIC DEVICES; MULTIPROCESSING SYSTEMS; PRESSES (MACHINE TOOLS); QUALITY CONTROL; SCHEDULING; SYSTEMS ANALYSIS;

CHIP MULTIPROCESSORS; DRAM; FAIRNESS; INTERFERENCE; MEMORY CONTROLLERS; MEMORY-LEVEL PARALLELISM; MULTICORE; PARALLEL PROCESSING; PRESSES; QUALITY OF SERVICE; RANDOM ACCESS MEMORY;

PROGRAM PROCESSORS;

EID: 63149087305     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2009.12     Document Type: Conference Paper

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