메뉴 건너뛰기




Volumn 6174 LNCS, Issue , 2010, Pages 24-40

ABC: An academic industrial-strength verification tool

Author keywords

equivalence checking; integrated sequential verification flow; logic synthesis; Model checking; simulation

Indexed keywords

BINARY LOGIC; EQUIVALENCE CHECKING; FLOW LOGIC; FORMAL VERIFICATIONS; HARDWARE DESIGN; INNOVATIVE ALGORITHMS; LOGIC SYNTHESIS; PUBLIC DOMAINS; SEQUENTIAL SYNTHESIS; VERIFICATION TOOLS;

EID: 77954979683     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-14295-6_5     Document Type: Conference Paper
Times cited : (698)

References (37)
  • 1
    • 0035208943 scopus 로고    scopus 로고
    • Min-area retiming on flexible circuit structures
    • Baumgartner, J., Kuehlmann, A.: Min-area retiming on flexible circuit structures. In: Proc. ICCAD '01, pp. 176-182 (2001)
    • (2001) Proc. ICCAD '01 , pp. 176-182
    • Baumgartner, J.1    Kuehlmann, A.2
  • 3
    • 77954966848 scopus 로고    scopus 로고
    • Berkeley Verification and Synthesis Research Center (BVSRC), http://www.bvsrc.org
  • 5
    • 16244421073 scopus 로고    scopus 로고
    • DAG-aware circuit compression for formal verification
    • Bjesse, P., Boralv, A.: DAG-aware circuit compression for formal verification. In: Proc. ICCAD '04, pp. 42-49 (2004)
    • (2004) Proc. ICCAD '04 , pp. 42-49
    • Bjesse, P.1    Boralv, A.2
  • 6
    • 33751411350 scopus 로고    scopus 로고
    • Automatic generalized phase abstraction for formal verification
    • Bjesse, P., Kukula, J.H.: Automatic generalized phase abstraction for formal verification. In: Proc. ICCAD '05, pp. 1076-1082 (2005)
    • (2005) Proc. ICCAD '05 , pp. 1076-1082
    • Bjesse, P.1    Kukula, J.H.2
  • 7
    • 0027832523 scopus 로고
    • Verification of large synthesized designs
    • Brand, D.: Verification of large synthesized designs. In: Proc. ICCAD '93, pp. 534-537 (1993)
    • (1993) Proc. ICCAD '93 , pp. 534-537
    • Brand, D.1
  • 10
    • 77954998279 scopus 로고    scopus 로고
    • The synergy between logic synthesis and equivalence checking
    • Keynote at
    • Brayton, R.: The synergy between logic synthesis and equivalence checking. In: Keynote at FMCAD'07 (2007), http://www.cs.utexas.edu/users/hunt/ FMCAD/2007/presentations/fmcad07-brayton.ppt
    • (2007) FMCAD'07
    • Brayton, R.1
  • 11
    • 0022769976 scopus 로고
    • Graph based algorithms for Boolean function manipulation
    • Bryant, R.E.: Graph based algorithms for Boolean function manipulation. IEEE TC 35(8), 677-691 (1986)
    • (1986) IEEE TC , vol.35 , Issue.8 , pp. 677-691
    • Bryant, R.E.1
  • 12
    • 70350043764 scopus 로고    scopus 로고
    • Speeding up model checking by exploiting explicit and hidden verification constraints
    • Cabodi, G., Camurati, P., Garcia, L., Murciano, M., Nocco, S., Quer, S.: Speeding up model checking by exploiting explicit and hidden verification constraints. In: Proc. DATE '09, pp. 1686-1691 (2009)
    • (2009) Proc. DATE '09 , pp. 1686-1691
    • Cabodi, G.1    Camurati, P.2    Garcia, L.3    Murciano, M.4    Nocco, S.5    Quer, S.6
  • 14
    • 33751405387 scopus 로고    scopus 로고
    • Reducing structural bias in technology mapping
    • Chatterjee, S., Mishchenko, A., Brayton, R., Wang, X., Kam, T.: Reducing structural bias in technology mapping. In: Proc. ICCAD '05, pp. 519-526 (2005), http://www.eecs.berkeley.edu/~alanmi/publications/2005/iccad05-map.pdf
    • (2005) Proc. ICCAD '05 , pp. 519-526
    • Chatterjee, S.1    Mishchenko, A.2    Brayton, R.3    Wang, X.4    Kam, T.5
  • 15
    • 84856140605 scopus 로고
    • Verification of sequential machines based on symbolic execution
    • Sifakis, J. (ed.) CAV 1989. Springer, Heidelberg
    • Coudert, O., Berthet, C., Madre, J.C.: Verification of sequential machines based on symbolic execution. In: Sifakis, J. (ed.) CAV 1989. LNCS, vol. 407. Springer, Heidelberg (1990)
    • (1990) LNCS , vol.407
    • Coudert, O.1    Berthet, C.2    Madre, J.C.3
  • 17
    • 77954961070 scopus 로고    scopus 로고
    • A single-instance incremental SAT formulation of proof- And counterexample-based abstraction
    • Een, N., Mishchenko, A., Amla, N.: A single-instance incremental SAT formulation of proof- and counterexample-based abstraction. In: Proc. IWLS'10 (2010)
    • (2010) Proc. IWLS'10
    • Een, N.1    Mishchenko, A.2    Amla, N.3
  • 18
    • 70349332327 scopus 로고    scopus 로고
    • WireMap: FGPA technology mapping for improved routability
    • Jang, S., Chan, B., Chung, K., Mishchenko, A.: WireMap: FGPA technology mapping for improved routability. In: Proc. FPGA '08, pp. 47-55 (2008)
    • (2008) Proc. FPGA '08 , pp. 47-55
    • Jang, S.1    Chan, B.2    Chung, K.3    Mishchenko, A.4
  • 19
    • 77955009139 scopus 로고    scopus 로고
    • A power optimization toolbox for logic synthesis and mapping
    • Jang, S., Chung, K., Mishchenko, A., Brayton, R.: A power optimization toolbox for logic synthesis and mapping. In: Proc. IWLS '09, pp. 1-8 (2009)
    • (2009) Proc. IWLS '09 , pp. 1-8
    • Jang, S.1    Chung, K.2    Mishchenko, A.3    Brayton, R.4
  • 20
    • 33845636607 scopus 로고    scopus 로고
    • Retiming and resynthesis: A complexity perspective
    • Jiang, J.-H.R., Brayton, R.: Retiming and resynthesis: A complexity perspective. IEEE Trans. CAD 25(12), 2674-2686 (2006), http://www.eecs.berkeley. edu/~brayton/publications/2006/tcad06-r&r.pdf
    • (2006) IEEE Trans. CAD , vol.25 , Issue.12 , pp. 2674-2686
    • Jiang, J.-H.R.1    Brayton, R.2
  • 21
    • 50249101190 scopus 로고    scopus 로고
    • Inductive equivalence checking under retiming and resynthesis
    • Jiang, J.-H.R., Hung, W.-L.: Inductive equivalence checking under retiming and resynthesis. In: Proc. ICCAD'07, pp. 326-333 (2007)
    • (2007) Proc. ICCAD'07 , pp. 326-333
    • Jiang, J.-H.R.1    Hung, W.-L.2
  • 22
    • 0036918496 scopus 로고    scopus 로고
    • Robust Boolean reasoning for equivalence checking and functional property verification
    • Kuehlmann, A., Paruthi, V., Krohm, F., Ganai, M.K.: Robust Boolean reasoning for equivalence checking and functional property verification. IEEE Trans. CAD 21(12), 1377-1394 (2002)
    • (2002) IEEE Trans. CAD , vol.21 , Issue.12 , pp. 1377-1394
    • Kuehlmann, A.1    Paruthi, V.2    Krohm, F.3    Ganai, M.K.4
  • 23
    • 33746763910 scopus 로고
    • Retiming synchronous circuitry
    • Leiserson, C.E., Saxe, J.B.: Retiming synchronous circuitry. Algorithmica 6, 5-35 (1991)
    • (1991) Algorithmica , vol.6 , pp. 5-35
    • Leiserson, C.E.1    Saxe, J.B.2
  • 26
    • 33846545005 scopus 로고    scopus 로고
    • DAG-aware AIG rewriting: A fresh look at combinational logic synthesis
    • Mishchenko, A., Chatterjee, S., Brayton, R.: DAG-aware AIG rewriting: A fresh look at combinational logic synthesis. In: Proc. DAC '06, pp. 532-536 (2006), http://www.eecs.berkeley.edu/~alanmi/publications/2006/dac06-rwr.pdf
    • (2006) Proc. DAC '06 , pp. 532-536
    • Mishchenko, A.1    Chatterjee, S.2    Brayton, R.3
  • 28
  • 29
  • 30
    • 77951556250 scopus 로고    scopus 로고
    • Global delay optimization using structural choices
    • Mishchenko, A., Brayton, R., Jang, S.: Global delay optimization using structural choices. In: Proc. FPGA'10, pp. 181-184 (2010)
    • (2010) Proc. FPGA'10 , pp. 181-184
    • Mishchenko, A.1    Brayton, R.2    Jang, S.3
  • 31
    • 77954962672 scopus 로고    scopus 로고
    • Magic: An industrial-strength logic optimization, technology mapping, and formal verification tool
    • Mishchenko, A., Een, N., Brayton, R.K., Jang, S., Ciesielski, M., Daniel, T.: Magic: An industrial-strength logic optimization, technology mapping, and formal verification tool. In: IWLS'10 (2010)
    • (2010) IWLS'10
    • Mishchenko, A.1    Een, N.2    Brayton, R.K.3    Jang, S.4    Ciesielski, M.5    Daniel, T.6
  • 33
    • 70350060045 scopus 로고    scopus 로고
    • Speculative reduction-based scalable redundancy identification
    • Mony, H., Baumgartner, J., Mishchenko, A., Brayton, R.: Speculative reduction-based scalable redundancy identification. In: Proc. DATE'09, pp. 1674-1679 (2009)
    • (2009) Proc. DATE'09 , pp. 1674-1679
    • Mony, H.1    Baumgartner, J.2    Mishchenko, A.3    Brayton, R.4
  • 36
    • 0010832726 scopus 로고    scopus 로고
    • CUDD v. 2.3.1
    • Somenzi, F.: BDD package. CUDD v. 2.3.1, http://vlsi.colorado.edu/~fabio/ CUDD/cuddIntro.html
    • BDD Package
    • Somenzi, F.1
  • 37
    • 0033712183 scopus 로고    scopus 로고
    • BDS: A BDD-based logic optimization system
    • Yang, C., Ciesielski, M., Singhal, V.: BDS: a BDD-based logic optimization system. In: Proc. DAC'00, pp. 92-97 (2000), http://www.ecs.umass. edu/ece/labs/vlsicad/bds/bds.html
    • (2000) Proc. DAC'00 , pp. 92-97
    • Yang, C.1    Ciesielski, M.2    Singhal, V.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.