메뉴 건너뛰기




Volumn , Issue , 2006, Pages 259-266

Scalable sequential equivalence checking across arbitrary design transformations

Author keywords

[No Author keywords available]

Indexed keywords

CHLORINE COMPOUNDS; MATHEMATICAL TRANSFORMATIONS; NONMETALS; SEQUENTIAL CIRCUITS; SILICON; SOLUTIONS;

EID: 49749112061     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2006.4380826     Document Type: Conference Paper
Times cited : (48)

References (28)
  • 1
    • 0004291229 scopus 로고    scopus 로고
    • Combinational and Sequential Equivalence Checking
    • Kluwer Academic Publishers
    • A. Kuehlmann and C. van Eijk, Combinational and Sequential Equivalence Checking, in Logic Synthesis and Verification. Kluwer Academic Publishers, 2004.
    • (2004) Logic Synthesis and Verification
    • Kuehlmann, A.1    van Eijk, C.2
  • 2
    • 16244370079 scopus 로고    scopus 로고
    • Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints
    • Nov
    • Z. Khasidashvili, M. Skaba, D. Kaiss, and Z. Hanna, "Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints," in ICCAD, Nov. 2004.
    • (2004) ICCAD
    • Khasidashvili, Z.1    Skaba, M.2    Kaiss, D.3    Hanna, Z.4
  • 3
    • 0036294466 scopus 로고    scopus 로고
    • Functional verification of the POWER4 micro-processor and POWER4 multiprocessor systems
    • Jan
    • J. Ludden et al., "Functional verification of the POWER4 micro-processor and POWER4 multiprocessor systems," IBM Journal of Research and Development, Jan. 2002.
    • (2002) IBM Journal of Research and Development
    • Ludden, J.1
  • 4
    • 84893769353 scopus 로고    scopus 로고
    • Sequential equivalence checking without state space traversal
    • March
    • C. A. J. van Eijk, "Sequential equivalence checking without state space traversal," in DATE, March 1998.
    • (1998) DATE
    • van Eijk, C.A.J.1
  • 5
    • 0000318151 scopus 로고
    • A theory and implementation of sequential hardware equivalence
    • Dec
    • C. Pixley, "A theory and implementation of sequential hardware equivalence," in TCAD, Dec. 1992.
    • (1992) TCAD
    • Pixley, C.1
  • 6
    • 0035248165 scopus 로고    scopus 로고
    • Theory of safe replacements for sequential circuits
    • Feb
    • V. Singhal, C. Pixley, A. Aziz, and R. Brayton, "Theory of safe replacements for sequential circuits," in TCAD, Feb. 2001.
    • (2001) TCAD
    • Singhal, V.1    Pixley, C.2    Aziz, A.3    Brayton, R.4
  • 7
    • 49749093283 scopus 로고    scopus 로고
    • SAT-based methods for sequential hardware equivalence verification without synchronization
    • Z. Khasidashvili and Z. Hanna, "SAT-based methods for sequential hardware equivalence verification without synchronization," in ICCAD, 2003.
    • (2003) ICCAD
    • Khasidashvili, Z.1    Hanna, Z.2
  • 8
    • 27944482543 scopus 로고    scopus 로고
    • H. Mony, J. Baumgartner, V. Paruthi, and R. Kanzelman, Exploiting suspected redundancy without proving it, in DAC, June 2005. Extended version available.
    • H. Mony, J. Baumgartner, V. Paruthi, and R. Kanzelman, "Exploiting suspected redundancy without proving it," in DAC, June 2005. Extended version available.
  • 9
    • 0029214276 scopus 로고    scopus 로고
    • V. Singhal, C. Pixley, R. L. Rudell, and R. K. Brayton, The validity of retiming sequential circuits, in DAC, 1995.
    • V. Singhal, C. Pixley, R. L. Rudell, and R. K. Brayton, "The validity of retiming sequential circuits," in DAC, 1995.
  • 10
    • 49749094254 scopus 로고    scopus 로고
    • A. Kuehlmann and J. Baumgartner, Transformation-based verification using generalized retiming, in CAV, July 2001.
    • A. Kuehlmann and J. Baumgartner, "Transformation-based verification using generalized retiming," in CAV, July 2001.
  • 12
    • 2542494639 scopus 로고    scopus 로고
    • SAT-based verification without state space traversal
    • November
    • P. Bjesse and K. Claessen, "SAT-based verification without state space traversal," in FMCAD, November 2000.
    • (2000) FMCAD
    • Bjesse, P.1    Claessen, K.2
  • 13
    • 0036918496 scopus 로고    scopus 로고
    • Robust Boolean reasoning for equivalence checking and functional property verification
    • Dec
    • A. Kuehlmann, V. Paruthi, F. Krohm, and M. Ganai, "Robust Boolean reasoning for equivalence checking and functional property verification," TCAD, Dec. 2002.
    • (2002) TCAD
    • Kuehlmann, A.1    Paruthi, V.2    Krohm, F.3    Ganai, M.4
  • 14
    • 85165857616 scopus 로고    scopus 로고
    • A. Mishchenko, S. Chatterjee, and R. Brayton, DAG-aware AIG rewriting: A fresh look at combinational logic synthesis, in DAC, July 2006.
    • A. Mishchenko, S. Chatterjee, and R. Brayton, "DAG-aware AIG rewriting: A fresh look at combinational logic synthesis," in DAC, July 2006.
  • 15
    • 33646412763 scopus 로고    scopus 로고
    • Maximal input reduction of sequential netlists via synergistic reparameterization and localization strategies
    • Oct
    • J. Baumgartner and H. Mony, "Maximal input reduction of sequential netlists via synergistic reparameterization and localization strategies," in CHARME, Oct. 2005.
    • (2005) CHARME
    • Baumgartner, J.1    Mony, H.2
  • 16
    • 49749089945 scopus 로고    scopus 로고
    • G. S. Manku, R. Hojati, and R. K. Brayton, Structural symmetry and model checking, in CAV, July 1998.
    • G. S. Manku, R. Hojati, and R. K. Brayton, "Structural symmetry and model checking," in CAV, July 1998.
  • 17
    • 33751411350 scopus 로고    scopus 로고
    • Automatic generalized phase abstraction for formal verification
    • Nov
    • P. Bjesse and J. Kukula, "Automatic generalized phase abstraction for formal verification," in ICCAD, Nov. 2005.
    • (2005) ICCAD
    • Bjesse, P.1    Kukula, J.2
  • 18
    • 49749142884 scopus 로고    scopus 로고
    • J. Baumgartner, A. Tripp, A. Aziz, V. Singhal, and F. Andersen, An abstraction algorithm for the verification of generalized C-slow designs, in CAV, July 2000.
    • J. Baumgartner, A. Tripp, A. Aziz, V. Singhal, and F. Andersen, "An abstraction algorithm for the verification of generalized C-slow designs," in CAV, July 2000.
  • 19
    • 49749112752 scopus 로고    scopus 로고
    • J. Baumgartner, A. Kuehlmann, and J. Abraham, Property checking via structural analysis, in CAV, July 2002.
    • J. Baumgartner, A. Kuehlmann, and J. Abraham, "Property checking via structural analysis," in CAV, July 2002.
  • 20
    • 49749132196 scopus 로고    scopus 로고
    • Efficient symbolic simulation via dynamic scheduling, don't caring, and case splitting
    • Oct
    • V. Paruthi, C. Jacobi, and K. Weber, "Efficient symbolic simulation via dynamic scheduling, don't caring, and case splitting," in CHARME, Oct. 2005.
    • (2005) CHARME
    • Paruthi, V.1    Jacobi, C.2    Weber, K.3
  • 21
    • 27944500344 scopus 로고    scopus 로고
    • REVERSE: Efficient sequential verification for retiming
    • M. Mneimneh and K. Sakallah, "REVERSE: Efficient sequential verification for retiming," in IWLS, 2003.
    • (2003) IWLS
    • Mneimneh, M.1    Sakallah, K.2
  • 22
    • 0029695303 scopus 로고    scopus 로고
    • On verifying the correctness of retimed circuits
    • Mar
    • S.-Y. Huang, K.-T. Cheng, and K.-C. Chen, "On verifying the correctness of retimed circuits," in GLSVLSI, Mar. 1996.
    • (1996) GLSVLSI
    • Huang, S.-Y.1    Cheng, K.-T.2    Chen, K.-C.3
  • 23
    • 33846572844 scopus 로고    scopus 로고
    • Sequential equivalence checking based on K-th invariants and circuit SAT solving
    • Dec
    • F. Lu and T. Cheng, "Sequential equivalence checking based on K-th invariants and circuit SAT solving," in HLDVT, Dec. 2005.
    • (2005) HLDVT
    • Lu, F.1    Cheng, T.2
  • 24
    • 2442542271 scopus 로고    scopus 로고
    • Exploiting state encoding for invariant generation in induction-based property checking
    • Jan
    • M. Wedler, D. Stoffel, and W. Kunz, "Exploiting state encoding for invariant generation in induction-based property checking," in ASP-DAC, Jan. 2004.
    • (2004) ASP-DAC
    • Wedler, M.1    Stoffel, D.2    Kunz, W.3
  • 25
    • 33646433328 scopus 로고    scopus 로고
    • Increasing the robustness of bounded model checking by computing lower bounds on the reachable states
    • Nov
    • M. Awedh and F. Somenzi, "Increasing the robustness of bounded model checking by computing lower bounds on the reachable states," in FMCAD, Nov. 2004.
    • (2004) FMCAD
    • Awedh, M.1    Somenzi, F.2
  • 26
    • 51549111292 scopus 로고    scopus 로고
    • TRANS: Efficient sequential verification of loop-free circuits
    • Z. Khasidashvili, J. Moondanos, and Z. Hanna, "TRANS: Efficient sequential verification of loop-free circuits," in HLDVT, 2002.
    • (2002) HLDVT
    • Khasidashvili, Z.1    Moondanos, J.2    Hanna, Z.3
  • 27
    • 27944462795 scopus 로고    scopus 로고
    • Scalable automated verification via expert-system guided transformations
    • Nov
    • H. Mony, J. Baumgartner, V. Paruthi, R. Kanzelman, and A. Kuehlmann, "Scalable automated verification via expert-system guided transformations," in FMCAD, Nov. 2004.
    • (2004) FMCAD
    • Mony, H.1    Baumgartner, J.2    Paruthi, V.3    Kanzelman, R.4    Kuehlmann, A.5
  • 28
    • 33646898170 scopus 로고    scopus 로고
    • Automatic formal verification of fused-multiply-add FPUs
    • March
    • C. Jacobi, K. Weber, V. Paruthi, and J. Baumgartner, "Automatic formal verification of fused-multiply-add FPUs," in DATE, March 2005.
    • (2005) DATE
    • Jacobi, C.1    Weber, K.2    Paruthi, V.3    Baumgartner, J.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.