A fault-tolerant and congestion-aware routing algorithm for Networks-on-Chip

Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010

Volumn , Issue , 2010, Pages 139-144

  Valinataj, Mojtaba ^a,b   Mohammadi, Siamak ^a   Plosila, Juha ^b   Liljeberg, Pasi ^b  

^a UNIVERSITY OF TEHRAN   (Iran)

^b UNIVERSITY OF TURKU   (Finland)

Author keywords

Fault tolerance; Network on Chip; Reconfiguration; Routing algorithm; Traffic

Indexed keywords

ADAPTIVENESS; CONGESTION-AWARE ROUTING; FAULT-TOLERANCE CAPABILITY; FAULT-TOLERANT; FAULT-TOLERANT ROUTING ALGORITHM; FAULTY LINKS; HARDWARE COST; HARDWARE OVERHEADS; MULTIPLE LINKS; NETWORK ON CHIP; NETWORKS ON CHIPS; ROUTING METHODS; VIRTUAL CHANNELS;

COMPUTER SIMULATION; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; MESH NETWORKING; NETWORK PERFORMANCE; ROUTERS; ROUTING ALGORITHMS; VLSI CIRCUITS;

QUALITY ASSURANCE;

EID: 77954937186     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DDECS.2010.5491798     Document Type: Conference Paper

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