Performance prediction of throughput-centric pipelined global interconnects with voltage scaling

International Workshop on System Level Interconnect Prediction, SLIP

Volumn , Issue , 2010, Pages 69-76

  Zhang, Yulei ^a   Buckwalter, James F ^a   Cheng, Chung Kuan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Performance prediction; Pipelined global interconnects; Throughput per energy area (TPEA); Voltage scaling

Indexed keywords

45NM NODE; COMPUTING CAPACITY; DESIGN FREEDOM; DESIGN OBJECTIVES; DIFFERENT PROCESS; EVALUATION FLOW; GLOBAL INTERCONNECTS; INTERCONNECT LATENCY; NEW DESIGN; NUMERICAL EXPERIMENTS; ON-CHIP GLOBAL INTERCONNECTS; PARALLEL COMPUTING ARCHITECTURE; PERFORMANCE PREDICTION; PIPELINED GLOBAL INTERCONNECTS; SCALED MODELS; TECHNOLOGY SCALING; VOLTAGE-SCALING;

DESIGN; ELECTRIC POWER SYSTEM INTERCONNECTION; FORECASTING; INTERCONNECTION NETWORKS; PARALLEL ARCHITECTURES;

THROUGHPUT;

EID: 77954918659     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1811100.1811118     Document Type: Conference Paper

References (21)

1. R. Ho, K. W. Mai, and M. A. Horowitz, "The Future of Wires, " Proc. IEEE, vol. 89, no. 4, pp. 490-504, April 2001.
2. A. Deutsch, P. W. Coteus, G. V. Kopcsay, H. H. Smith, C. W. Surovic, B. L. Krauter, D. C. Edelstein, and P. L. Restle, "On-Chip Wiring Design Challenges for Gigahertz Operation, " Proc. IEEE, vol. 89, no. 4, pp. 529-555, April 2001.
3. Semiconductor Industry Association, "International Technology Roadmap for Semiconductors, " in http://www.itrs.net, 2007, 2008 Update.
4. D. Sylvester and K. Keutzer, "A Global Wiring Paradigm for Deep Submicron Design, " IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 19, no. 2, pp. 242-252, Feb 2000.
5. N. Magen, A. Kolodny, U. Weiser, and N. Shamir, "Interconnect-Power Dissipation in a Microprocessor, " in Proc. Int. Workshop on System Level Interconnect Prediction, Paris, France, Feb 2004, pp. 7-13.
6. Y. Zhang, X. Hu, A. Deutsch, A. E. Engin, J. F. Buckwalter, and C.-K. Cheng, "Prediction of High-Performance On-Chip Global Interconnection, " in Proc. of the Intl. Workshop on System Level Interconnect Prediction, San Francisco, CA, Jul 2009, pp. 61-68.
7. B. Kim and V. Stojanovic, "A 4Gb/s/ch 356fJ/b 10mm Equalized On-Chip Interconnect with Nonlinear Charge-Injecting Transmit Filter and Transimpedance Receiver in 90nm CMOS, " in Proc. IEEE Int. Solid-State Circuits Conf., Feb 2009, pp. 66-68.
8. H. Shah, P. Shiu, B. Bell, M. Aldredge, N. Sopory, and J. Davis, "Repeater Insertion and Wire Sizing Optimization for Throughput-Centric VLSI Global Interconnects, " in Proc. IEEE/ACM International Conference on Computer-Aided Design, 2002, pp. 280-284.
9. A. Jantsch and H. Tenhunen, Eds., Networks on Chip. Kluwer Academic Publishers, 2003.
10. S. Heo and K. Asanovic, "Replacing Global Wires with an On-Chip Network: A Power Analysis, " in Proc. IEEE Intl. Symp. on Low Power Elec. Design, Aug 2005, pp. 369-374.
11. J. Xu and W. Wolf, "A Wave-Pipelined On-Chip Interconnect Structure for Networks-on-Chips, " in Proc. IEEE Symp. on High Performance Interconnects, Aug 2003, pp. 10-14.
12. V. Deodhar, "Throughput-Centric Wave-Pipelined Interconnect Circuits for Gigascale Integration, " in PhD Thesis, Georgia Institute of Technology, 2005.
13. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, 1990.
14. Arizona State University, "Predictive Technology Model (PTM), " in http://ptm.asu.edu/.
15. L. Zhang, H. Chen, B. Yao, K. Hamilton, and C. Cheng, "Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals, " in Proc. IEEE Int. Symp. Quality Electron. Design, San Jose, CA, Mar 2007, pp. 251-256.
16. S. Sim, S. Krishnan, D. Petranovic, and N. Arora, "A Unified RLC Model for High-Speed On-Chip Interconnects, " IEEE Trans. Electron Devices, vol. 50, no. 6, pp. 1501-1510, June 2003.
17. P. Kapur, G. Chandra, and K. Saraswat, "Power Estimation in Global Interconnects and Its Reduction Using a Novel Repeater Optimization Methodology, " in Proc. IEEE/ACM Design Automation Conf., 2002, pp. 461-466.
18. J. Rabaey, Low Power Design Essentials. Springer, 2009.
19. MATLAB, in The MathWorks, www.mathworks.com, R2007a.
20. V. V. Deodhar and J. A. Davis, "Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects, " IEEE Trans. on Circuits and Systems I, vol. 55, no. 4, pp. 1023-1030, May 2008.
21. R. Nagpal, A. Madan, A. Bhardwaj, and Y. N. Srikant, "INTACTE: An Interconnect Area, Delay, and Energy Estimation Tool for Microarchitectural Explorations, " in Proc. ACM CASES' 07, 2007, pp. 238-247.