A comparison of precharge policies with modern DRAM architectures

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2002, Pages 823-826

  Alakarhu, Juha ^a   Niittylahti, Jarkko ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE SIZE; CACHE SYSTEMS; DESIGN ISSUES; DRAM ARCHITECTURES; DRAM MEMORIES; MEMORY SPEED; MEMORY SYSTEMS; PRE-CHARGE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 47749155036     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2002.1046301     Document Type: Conference Paper

References (8)

1. Wei-fen Lin, Steven K. Reinhardt, and Doug Burger, "Designing a modern memory hierarchy with hardware prefetching," IEEE Trans. Computers, vol.50, no.11, pp. 1202-1218, November 2001.
2. Juha Alakarhu and Jarkko Niittylahti, "DRAM simulator for design and analysis of digital systems," Microprocessors and Microsystems, vol.26, no.4, pp. 189-198, May 2002.
3. MindShare, Direct Rambus Architecture and Measurements.
4. Vinodh Cuppu, Bruce Jacob, Brian Davis, and Trevor Mudge, "High-performance DRAMs in workstation environments," IEEE Trans. Computers, vol.50, no.11, pp. 1133-1153, November 2001.
5. Brian Thomas Davis, Modern DRAM Architectures, Ph.D. thesis, The University of Michigan, 2001.
6. Doug Burger and Todd M. Austin, "The Simple Scalar tool set, version 2.0," Tech. Rep., Computer Sciences Department, University of Wisconsin, June 1997.
7. Micron Technology Inc., Double Data Rate (DDR) SDRAM 256Mb:x4, x8, xl6 Preliminary, April 2001.
8. Rambus Inc., Direct RDRAM 256/288-Mbit (512Kxl6/18x32s) Preliminary Information, June 2000.