-
1
-
-
84939573910
-
Differential power analysis
-
P. Kocher, J. Jaffe, and B. Jun, "Differential Power Analysis," Lecture Notes in Computer Science, vol. 1666, pp. 388-397, 1999.
-
(1999)
Lecture Notes in Computer Science
, vol.1666
, pp. 388-397
-
-
Kocher, P.1
Jaffe, J.2
Jun, B.3
-
2
-
-
43749116669
-
FPGA core watermarking based on power signature analysis
-
Bangkok, Thailand, Dec
-
D. Ziener and J. Teich, "FPGA Core Watermarking Based on Power Signature Analysis," in Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2006), Bangkok, Thailand, Dec. 2006, pp. 205-212.
-
(2006)
Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2006)
, pp. 205-212
-
-
Ziener, D.1
Teich, J.2
-
3
-
-
43449102491
-
Power signature watermarking of IP cores for FPGAs
-
April
-
D. Ziener and J. Teich, "Power Signature Watermarking of IP Cores for FPGAs," Journal of Signal Processing Systems, vol. 51, no. 1, pp. 123-136, April 2008.
-
(2008)
Journal of Signal Processing Systems
, vol.51
, Issue.1
, pp. 123-136
-
-
Ziener, D.1
Teich, J.2
-
4
-
-
0036384096
-
Dynamic power consumption in Virtex-II FPGA family
-
New York, NY, USA: ACM Press
-
L. Shang, A. S. Kaviani, and K. Bathala, "Dynamic power consumption in Virtex-II FPGA family," in FPGA '02: Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays. New York, NY, USA: ACM Press, 2002, pp. 157-164.
-
(2002)
FPGA '02: Proceedings of the 2002 ACM/SIGDA Tenth International Symposium on Field-programmable Gate Arrays
, pp. 157-164
-
-
Shang, L.1
Kaviani, A.S.2
Bathala, K.3
-
5
-
-
0026853681
-
Low-power CMOS digital design
-
A. Chandrakasan, S. Sheng, and R. Brodersen, "Low-power CMOS digital design," IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 473-484, 1992.
-
(1992)
IEEE Journal of Solid-state Circuits
, vol.27
, Issue.4
, pp. 473-484
-
-
Chandrakasan, A.1
Sheng, S.2
Brodersen, R.3
-
7
-
-
40949098849
-
-
[Online]. Available
-
Digilent, Inc. Spartan-3 board. S3BOARD.cfm. [Online]. Available: www.digilentinc.com/info.
-
Spartan-3 Board. S3BOARD.cfm
-
-
-
9
-
-
0032314638
-
Signature hiding techniques for FPGA intellectual property protection
-
J. Lach, W. H. Mangione-Smith, and M. Potkonjak, "Signature Hiding Techniques for FPGA Intellectual Property Protection," in proceedings of ICCAD, 1998, pp. 186-189.
-
(1998)
Proceedings of ICCAD
, pp. 186-189
-
-
Lach, J.1
Mangione-Smith, W.H.2
Potkonjak, M.3
-
10
-
-
0035472848
-
Constraint-based watermarking techniques for design IP protection
-
Kahng, Lach, Mangione-Smith, Mantik, Markov, Potkonjak, Tucker, Wang, and Wolfe, "Constraint-Based Watermarking Techniques for Design IP Protection," IEEETCAD: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, 2001.
-
(2001)
IEEETCAD: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.20
-
-
Kahng1
Lach2
Mangione-Smith3
Mantik4
Markov5
Potkonjak6
Tucker7
Wang8
Wolfe9
-
11
-
-
40949162594
-
Intellectual property protection using watermarking partial scan chains for sequential logic test generation
-
D. Kirovski and M. Potkonjak, "Intellectual Property Protection Using Watermarking Partial Scan Chains For Sequential Logic Test Generation," in ICCAD, 1998.
-
(1998)
ICCAD
-
-
Kirovski, D.1
Potkonjak, M.2
-
12
-
-
0032320166
-
Intellectual property protection by watermarking combinational logic synthesis solutions
-
D. Kirovski, Y.-Y. Hwang, M. Potkonjak, and J. Cong, "Intellectual property protection by watermarking combinational logic synthesis solutions," in proceedings of ICCAD, 1998, pp. 194-198.
-
(1998)
Proceedings of ICCAD
, pp. 194-198
-
-
Kirovski, D.1
Hwang, Y.-Y.2
Potkonjak, M.3
Cong, J.4
-
13
-
-
0031635593
-
Robust IP Watermarking methodologies for physical design
-
A. B. Kahng, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H.Wang, and G. Wolfe, "Robust IP Watermarking Methodologies for Physical Design," in Design Automation Conference, 1998, pp. 782-787.
-
(1998)
Design Automation Conference
, pp. 782-787
-
-
Kahng, A.B.1
Mantik, S.2
Markov, I.L.3
Potkonjak, M.4
Tucker, P.5
Wang, H.6
Wolfe, G.7
-
14
-
-
43449090780
-
Identifying FPGA IP-cores based on lookup table content analysis
-
Madrid, Spain, Aug
-
D. Ziener, S. Aßmus, and J. Teich, "Identifying FPGA IP-Cores based on Lookup Table Content Analysis," in Proceedings of 16th International Conference on Field Programmable Logic and Applications, Madrid, Spain, Aug. 2006, pp. 481-486.
-
(2006)
Proceedings of 16th International Conference on Field Programmable Logic and Applications
, pp. 481-486
-
-
Ziener, D.1
Aßmus, S.2
Teich, J.3
-
15
-
-
51849146248
-
Verifying the authenticity of chip designs with the DesignTag system
-
T. Kean, D. McLaren, and C. Marsh, "Verifying the authenticity of chip designs with the DesignTag system," in IEEE International Workshop on Hardware-Oriented Security and Trust, 2008. HOST 2008, 2008, pp. 59-64.
-
(2008)
IEEE International Workshop on Hardware-oriented Security and Trust, 2008. HOST 2008
, pp. 59-64
-
-
Kean, T.1
Mclaren, D.2
Marsh, C.3
-
16
-
-
43449112156
-
Evaluation of Watermarking methods for FPGA-based IP-cores
-
Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, Mar
-
D. Ziener and J. Teich, "Evaluation of Watermarking methods for FPGA-based IP-cores," University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, Tech. Rep. 01-2006, Mar. 2006.
-
(2006)
University of Erlangen-Nuremberg, Tech. Rep. 01-2006
-
-
Ziener, D.1
Teich, J.2
-
17
-
-
79551520399
-
-
Virtex-ii platform fpgas: Complete data sheet. ds031.pdf, [Online]. Available
-
Xilinx, Inc. Virtex-ii platform fpgas: Complete data sheet. ds031.pdf. [Online]. Available: direct.xilinx.com/bvdocs/publications.
-
Xilinx, Inc.
-
-
-
18
-
-
77954249261
-
-
Opencores.org, "Opencores," URL:www.opencores.org.
-
Opencores
-
-
|