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Volumn , Issue , 2010, Pages 238-244

Using the power side channel of FPGAs for communication

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS; ENCODING (SYMBOLS); PROGRAM DEBUGGING; SIGNAL ENCODING;

EID: 77954286116     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2010.43     Document Type: Conference Paper
Times cited : (22)

References (18)
  • 3
    • 43449102491 scopus 로고    scopus 로고
    • Power signature watermarking of IP cores for FPGAs
    • April
    • D. Ziener and J. Teich, "Power Signature Watermarking of IP Cores for FPGAs," Journal of Signal Processing Systems, vol. 51, no. 1, pp. 123-136, April 2008.
    • (2008) Journal of Signal Processing Systems , vol.51 , Issue.1 , pp. 123-136
    • Ziener, D.1    Teich, J.2
  • 7
    • 40949098849 scopus 로고    scopus 로고
    • [Online]. Available
    • Digilent, Inc. Spartan-3 board. S3BOARD.cfm. [Online]. Available: www.digilentinc.com/info.
    • Spartan-3 Board. S3BOARD.cfm
  • 9
    • 0032314638 scopus 로고    scopus 로고
    • Signature hiding techniques for FPGA intellectual property protection
    • J. Lach, W. H. Mangione-Smith, and M. Potkonjak, "Signature Hiding Techniques for FPGA Intellectual Property Protection," in proceedings of ICCAD, 1998, pp. 186-189.
    • (1998) Proceedings of ICCAD , pp. 186-189
    • Lach, J.1    Mangione-Smith, W.H.2    Potkonjak, M.3
  • 11
    • 40949162594 scopus 로고    scopus 로고
    • Intellectual property protection using watermarking partial scan chains for sequential logic test generation
    • D. Kirovski and M. Potkonjak, "Intellectual Property Protection Using Watermarking Partial Scan Chains For Sequential Logic Test Generation," in ICCAD, 1998.
    • (1998) ICCAD
    • Kirovski, D.1    Potkonjak, M.2
  • 12
    • 0032320166 scopus 로고    scopus 로고
    • Intellectual property protection by watermarking combinational logic synthesis solutions
    • D. Kirovski, Y.-Y. Hwang, M. Potkonjak, and J. Cong, "Intellectual property protection by watermarking combinational logic synthesis solutions," in proceedings of ICCAD, 1998, pp. 194-198.
    • (1998) Proceedings of ICCAD , pp. 194-198
    • Kirovski, D.1    Hwang, Y.-Y.2    Potkonjak, M.3    Cong, J.4
  • 16
    • 43449112156 scopus 로고    scopus 로고
    • Evaluation of Watermarking methods for FPGA-based IP-cores
    • Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, Mar
    • D. Ziener and J. Teich, "Evaluation of Watermarking methods for FPGA-based IP-cores," University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, Tech. Rep. 01-2006, Mar. 2006.
    • (2006) University of Erlangen-Nuremberg, Tech. Rep. 01-2006
    • Ziener, D.1    Teich, J.2
  • 17
    • 79551520399 scopus 로고    scopus 로고
    • Virtex-ii platform fpgas: Complete data sheet. ds031.pdf, [Online]. Available
    • Xilinx, Inc. Virtex-ii platform fpgas: Complete data sheet. ds031.pdf. [Online]. Available: direct.xilinx.com/bvdocs/publications.
    • Xilinx, Inc.
  • 18
    • 77954249261 scopus 로고    scopus 로고
    • Opencores.org, "Opencores," URL:www.opencores.org.
    • Opencores


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.