FPGA core watermarking based on power signature analysis

Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006

Volumn , Issue , 2006, Pages 205-212

  Ziener, Daniel ^a   Teich, Jürgen ^b  

^a FRAUNHOFER INSTITUTE FOR INTEGRATED CIRCUITS IIS   (Germany)

^b UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DIGITAL WATERMARKING; PHASE NOISE; PROBABILITY;

POWER SIGNATURE ANALYSIS; POWER SUPPLY PINS; WATERMARKED CORE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 43749116669     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2006.270313     Document Type: Conference Paper

References (15)

1. Xilinx, Inc. Next-Generation Virtex Family From Xilinx to top one Billion Transistor Mark. 03131_nextgen.htm. [Online]. Available: www.xilinx.corn/prs- ris/silicon_vir/
2. L. Boney, A. H. Tewfik, and K. N. Hamdy, "Digital watermarks for audio signals," in International Conference on Multimedia Computing and Systems, 1996, pp. 473-480. [Online]. Available: citeseer.ist.psu.edu/ boney96digital.html
3. J. Lach, W. H. Mangione-Smith, and M. Potkonjak, "Signature hiding techniques for FPGA intellectual property protection," in proceedings of ICCAD, 1998, pp. 186-189. [Online]. Available: citeseer.ist.psu.edu/ lach98signature.html
4. Kahng, Lach, Mangione-Smith., Mantik, Markov, Potkonjak, Tucker, Wang, and Wolfe, "Constraint-based watermarking techniques for design IP protection," IEEE TCAD: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, 2001. [Online]. Available: citeseer.ist.psu.edu/kahng01constraintbased.html
5. D. Kirovski and M. Potkonjak, "Intellectual, property protection using watermarking partial scan chains for sequential logic test generation," in ICCAD, 1998. [Online]. Available: citeseer.ist.psu.edu/218548.html
6. D. Kirovski, Y.-Y. Hwang, M. Potkonjak, and J. Cong, "Intellectual property protection by watermarking combinational logic synthesis solutions," in proceedings of ICCAD, 1.998, pp. 194-198. [Online]. Available: citeseer.ist.psu.edu/article/kirovski98intellectual.html
7. A. B. Kahng, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang, and G. Wolfe, "Robust IP watermarking methodologies for physical design," in Design Automation Conference, 1998, pp. 782-787. [Online]. Available: citeseer.ist.psu.edu/kahng98robust.html
8. P. Kocher, J. Jaffe, and B. Jun, "Differential power analysis," Lecture Notes in Computer Science, vol. 1666, pp. 388-397, 1999. [Online]. Available: citeseer.ist.psu.edu/kocher99differential.html
9. D. Agrawal, B. Archambeault, J. R. Rao, and P. Rohatgi, "The em side-channel(s)," in CHES '02: Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems. London, UK: Springer-Verlag, 2003, pp. 29-45.
10. A. Chandrakasan, S. Sheng, and R. Brodersen, "Low-Power CMOS Digital Design," 1992. [Online]. Available: citeseer.ist.psu.edu/ chandrakasan95low.html
11. L. Shang, A. S. Kaviani, and K. Bathala, "Dynamic power consumption in Virtex-II FPGA family," in FPGA '02: Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays. New York, NY, USA: ACM Press, 2002, pp. 157-164.
12. Xilinx, Inc. Virtex-ii. platform fpgas: Complete data sheet, ds031.pdf. [Online]. Available: direct.xilinx.com/bvdocs/publications
13. Digilent, Inc. Spartan-3 board. S3BOARD.cfm. [Online]. Available: www.digi.lentinc.com/info
14. Opencores.org. Basic des crypto core: Overview, overview. [Online]. Available: www.opencores.org/projects.cgi/webAasicdes
15. D. S. Taubman and M. W. Marcellin, JPEG 2000: Image Compression Fundamentals, Standards and Practice. Norwell, MA, USA: Kluwer Academic Publishers, 2001.