Gated diode investigation of bias temperature instability in high-κ FinFETs

IEEE Electron Device Letters

Volumn 31, Issue 7, 2010, Pages 653-655

  Young, Chadwin D ^a   Neugroschel, Arnost ^b   Matthews, Kenneth ^c   Smith, Casey ^a   Heh, Dawei ^a,d   Park, Hokyung ^a   Hussein, Muhammad M ^a   Taylor, William ^a   Bersuker, Gennadi ^a  

^a SEMATECH   (United States)

^b UNIVERSITY OF FLORIDA   (United States)

^c SVTC Technologies   (United States)

^d NATIONAL NANO DEVICE LABORATORIES   (Taiwan)

Author keywords

Bias temperature instability (BTI); charge pumping; DCIV; FinFET; hafnium; high

Indexed keywords

BIAS TEMPERATURE INSTABILITY; CHARGE PUMPING; FINFETS; GATE INTERFACE; GATE STACKS; GATED DIODES; INTERFACE TRAP DENSITY; INTERFACE TRAP GENERATION; NEGATIVE BIAS; PLANAR DEVICES; POSITIVE BIAS; PRE-STRESS; SI-H BONDS;

DIODES; HAFNIUM; PUMPS; SILICON COMPOUNDS;

STABILITY;

EID: 77954145797     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2010.2049635     Document Type: Article

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