Improved interface characterization technique for high-k/metal gated MugFETs utilizing a gated diode structure

Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010

Volumn , Issue , 2010, Pages 68-69

  Young, C D ^a   Neugroschel, A ^b   Matthews, K ^c   Smith, C ^a   Park, H ^a   Hussain, M M ^a   Majhi, P ^d   Bersuker, G ^a  

^a SEMATECH   (United States)

^b UNIVERSITY OF FLORIDA   (United States)

^c SVTC ^*  (United States)

^d INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIAS TEMPERATURE INSTABILITY; BURIED OXIDE LAYERS; CHARGE PUMPING; CMOS PROCESSING; FINFETS; FUTURE TECHNOLOGIES; GATED DIODES; INTERFACE CHARACTERIZATION; INTERFACE STATE; LONG-TERM OPERATION; MULTI-GATE FIELD EFFECT TRANSISTORS; OXIDE CHARGING; PLANAR DEVICES; STRESS-INDUCED DEGRADATION; SUBSTRATE CONTACT; TEST STRUCTURE; THREE-DIMENSIONAL (3D); TIME EVOLUTIONS;

CRYSTAL ORIENTATION; DIODES; ELECTRONIC EQUIPMENT TESTING; FINS (HEAT EXCHANGE); GATE DIELECTRICS; GATES (TRANSISTOR); INTEGRATED CIRCUITS; THREE DIMENSIONAL;

FIELD EFFECT TRANSISTORS;

EID: 77957929844     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2010.5488943     Document Type: Conference Paper

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