Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs

Proceedings of the 2010 IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum, IPDPSW 2010

Volumn , Issue , 2010, Pages

  Hübner, Michael ^a,b,c   Göhringer, Diana ^a,b,c   Noguera, Juanjo ^a,b,c   Becker, Jürgen ^a,b,c  

^a Fraunhofer FOM ^*  (Germany)

^b KARLSRUHE INSTITUTE OF TECHNOLOGY   (Germany)

^c XILINX INC   (United States)

Author keywords

Dynamic and partial processor reconfiguration; FPGA; Internal configuration access port (ICAP); Processor adaptation

Indexed keywords

ACCESS PORTS; ADAPTIVE SYSTEM DESIGN; CHIP AREAS; DATA PATHS; DATA THROUGHPUT; DYNAMIC AND PARTIAL RECONFIGURATION; FAST DYNAMICS; FPGA; HARDWARE DESIGN; HARDWARE DRIVERS; HARDWARE OVERHEADS; HARDWARE RESOURCES; INTERNAL ARCHITECTURE; INTERNAL CONFIGURATION ACCESS PORTS; NOVEL METHODOLOGY; POWER CONSUMPTION; PROCESSOR CORES; RUNTIMES; TEMPORAL PARTITIONING;

ADAPTIVE SYSTEMS; DISTRIBUTED PARAMETER NETWORKS; NANOTECHNOLOGY;

COMPUTER ARCHITECTURE;

EID: 77954056866     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPSW.2010.5470736     Document Type: Conference Paper

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