Register file partitioning and recompilation for register file power reduction

ACM Transactions on Design Automation of Electronic Systems

Volumn 15, Issue 3, 2010, Pages

  Guan, Xuan ^a   Fei, Yunsi ^a  

^a UNIVERSITY OF CONNECTICUT   (United States)

Author keywords

Compilers; Low power design; Processor architectures; Register file partitioning

Indexed keywords

AREA OVERHEAD; BIT LINES; COLD REGIONS; EFFECTIVE ALGORITHMS; EMBEDDED PROCESSORS; ENERGY CONSUMPTION; EXECUTION TIME; GRAPH PARTITIONING PROBLEMS; HOT REGIONS; LOW-POWER DESIGN; OPTIMAL RESULTS; POWER REDUCTIONS; POWER SAVINGS; PROCESSOR ARCHITECTURES; RECOMPILATION; REGISTER FILES; SIMPLESCALAR; WORKING TIME;

COMPUTER ARCHITECTURE; ELECTRIC LOAD FORECASTING; GRAPH THEORY; INTERACTIVE COMPUTER SYSTEMS; NANOTECHNOLOGY;

PROGRAM COMPILERS;

EID: 77953597369     PISSN: 10844309     EISSN: 15577309     Source Type: Journal    
DOI: 10.1145/1754405.1754409     Document Type: Article

References (32)

1. ARM10. ARM10 processor. http://www.arm.com/products/CPUs/families/ ARM10EFamily.html.
2. ARM7. ARM7 processor. http://www.arm.com/products/CPUs/ARM7TDMI.html.
3. AYALA, J. L. AND VEIDENBAUM, A. 2002. Reducing register file energy consumption using compiler support. In Proceedings of the Workshop on Application-Specific Processors.
4. AYALA, J. L., VEIDENBAUM, A., AND VALLEJO, M. L. 2003. Power-Aware compilation for register file energy reduction. Int. J. Parall. Program. 31, 6, 451-467.
5. BENINI, L., KANDEMIR, M., AND RAMANUJAM, J., EDS. 2003. Compilers and Operating Systems for Low Power. Kluwer Academic Publishers, Boston, MA.
6. BORKAR, S. 2003. Getting gigascale chips: Challenges and opportunities in continuing Moore's law. ACM Queue 1, 7, 26-33.
7. CHINNERY, D. AND KEUTZER, K., EDS. 2007. Closing the Power Gap between ASIC and Custom: Tools and Techniques for Low Power Design. Springer.
8. CHUNG, S. W. AND SKADRON, K. 2006. A novel software solution for localized thermal problems. In Proceedings of the International Symposium on Parallel and Distributed Processing and Applications. 63-74.
9. DIOPSIS. DIOPSIS 740. http://www.atmel.com/dyn/resources/.
10. FLAUTNER, K., KIM, N. S., MARTIN, S., BLAAUW, D., AND MUDGE, T. 2002. Drowsy caches: Simple techniques for reducing leakage power. In Proceedings of the International Symposium on Computer Architecture. 148-157.
11. GOMEZ, M. AND SANTONJA., V. 2002. Characterizing temporal locality in I/O workload. In Proceedings of the International Symposium on Performance Evaluation Computer and Telecommunication Systems. 76-82.
12. GUAN, X. AND FEI, Y. 2008. Reducing power consumption of embedded processors through register file partitioning and compiler support. In Proceedings of the Conference on Application-Specific Systems, Architectures and Processors. 269-274.
13. HU, Z. AND MARTONOSI, M. 2000. Reducing register file power consumption by exploiting value lifetime characteristics. In Proceedings of the Workshop on Complexity-Effective Design.
14. JAIN, M. K., BALAKRISHNAN, M., AND KUMAR, A. 2002. An efficient technique for exploring register file size in ASIP synthesis. In Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. 252-261.
15. LAMBRECHTS, A., RAGHAVAN, P., LEROY, A., TALAVERA, G., AA, T. V., JAYAPALA, M., CATTHOOR, F., VERKEST, D., DECONINCK, G., CORPORAAL, H., ROBERT, F., AND CARRABINA, J. 2005. Power breakdown analysis for a heterogeneous NoC platform running a video application. In Proceedings of the Conference on Application-Specific Systems, Architectures and Processors. 179-184.
16. LIN, T.-J., CHEN, S.-K., KUO, Y.-T., LIU, C.-W., AND HSIAO, P.-C. 2008. Design and implementation of a high-performance and complexity-effective VLIW DSP for multimedia applications. J. VLSI Signal Process. 51, 3, 209-223.
17. MiBench. MiBench applications. http://www.eecs.umich.edu/mibench/.
18. PARK, J., LEE, J., AND MOON, S. M. 2001. Register allocation for banked register file. ACM Special Interest Group Program. Lang. 36, 8, 39-47.
19. PARK, S., SHRIVASTAVA, A., DUTT, N., AND NICOLAU, A. 2008. Register file power reduction using bypass sensitive compiler. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 27, 6, 1155-1159.
20. POUWELSE, J., LANGENDOEN, K., AND SIPS, H. 2001. Dynamic voltage scaling on a low-power microprocessor. In Proceedings of the International Conference on Mobile Computing and Networking. 251-259.
21. RABAEY, J. AND PEDRAM, M., EDS. 1996. Low Power Design Methodologies. Kluwer Academic Publishers, Norwell, MA.
22. RAVINDRAN, R. A., SENGER, R. M., MARSMAN, E. D., DASIKA, G. S., GUTHAUS, M. R., MAHLKE, S. A., AND BROWN, R. B. 2005. Partitioning variables across register windows to reduce spill code in a low-power processor. IEEE Trans. Comput. 54, 8, 998-1012.
23. SAIT, S. M. AND YOUSSEF, H. 1999. VLSI Physical Design Automation: Theory and Practice. World Scientific, Singapore.
24. SCHUSTER, T., BOUGARD, B., RAGHAVAN, P., R. PRIEWASSER, NOVO, D., PERRE, L. V., AND CATTHOOR, F. 2007. Design of a low power pre-synchronization ASIP for multimode SDR terminals. In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. 322-332.
25. SEARLES, M., WHALLEY, D., AND TYSON, G. 2006. Exploitation of a large data register file. In Proceedings of the International Conference on Languages, Compilers, and Tools for Embedded Systems. 252-261.
26. SHRIVASTAVA, A., EARLIE, E., DUTT, N., AND NICOLAU, A. 2004. Operation tables for scheduling in the presence of incomplete bypassing. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis. 194-199.
27. SIMPLESCALAR. Simplescalar. http://www.simplescalar.com/.
28. SPEC2000. SPEC2000 appplications. http://www.spec.org.
29. SU, H., LIU, F., DEVGAN, A., ACAR, E., AND NASSIF, S. 2003. Full chip leakage estimation considering power supply and temperature variations. In Proceedings of the International Symposium on Low Power Electronics and Design. 78-83.
30. TSENG, J. H. AND ASANOVIC, K. 2000. Energy-Efficient register access. In Proceedings of the Conference on Integrated Circuits and Systems Design. 377-382.
31. VIERI, C. 1995. Pendulum: A reversible computer architecture. M.S. thesis, MIT Artificial Intelligence Laboratory.
32. ZHAO, X. M. AND YE, Y. Z. 2002. Structure configuration of low power register file using energy model. In Proceedings of the Asia Pacific Conference on ASIC. 41-44.