An efficient technique for exploring register file size in ASIP synthesis

Proceedings of the 2002 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES '02

Volumn , Issue , 2002, Pages 252-261

  Jain, Manoj Kumar ^a   Balakrishnan, M ^a   Kumar, Anshul ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

ASIP synthesis; Design space exploration; Global analysis; Instruction scheduling; Liveness analysis; Register file; Register spill; Retargetable estimation; Storage exploration

Indexed keywords

GLOBAL ANALYSIS; INSTRUCTION SCHEDULING; LIVENESS; REGISTER FILE; REGISTER FILES; RETARGETABLE; SYNTHESIS DESIGN;

DESIGN; ESTIMATION; HAZARDOUS MATERIALS SPILLS; PROGRAM COMPILERS; SCHEDULING; SPACE RESEARCH; SYNTHESIS (CHEMICAL);

EMBEDDED SYSTEMS;

EID: 77953004079     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/581630.581671     Document Type: Conference Paper

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