Design and implementation of a high-performance and complexity-effective VLIW DSP for multimedia applications

Journal of Signal Processing Systems

Volumn 51, Issue 3, 2008, Pages 209-223

  Lin, Tay Jyi ^a   Chen, Shin Kai ^a   Kuo, Yu Ting ^a   Liu, Chih Wei ^a   Hsiao, Pi Chen ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

Digital signal processor; Instruction encoding; Micro architecture; Register organization; VLIW

Indexed keywords

HIERARCHICAL SYSTEMS; LOGIC DESIGN; MULTIMEDIA SYSTEMS; PATTERN RECOGNITION; SEMICONDUCTING SILICON;

INSTRUCTION ENCODING; MICROARCHITECTURE; PING-PONG REGISTERS; REGISTER ORGANIZATION;

DIGITAL SIGNAL PROCESSORS;

EID: 43149113433     PISSN: 19398018     EISSN: 19398115     Source Type: Journal    
DOI: 10.1007/s11265-007-0061-x     Document Type: Article

References (32)

1. 1. P. Lapsley, J. Bier, and E. A. Lee, “DSP Processor Fundamentals-Architectures and Features,” IEEE Press, 1996.
2. 2. Y. H. Hu, “Programmable Digital Signal Processors—Architecture, Programming, and Applications,” Marcel Dekker, 2002.
3. 3. J. A. Fisher, P. Faraboschi, and C. Young, “Embedded Computing—A VLIW Approach to Architecture, Compiler, and Tools,” Morgan Kaufmann, 2005.
4. 4. S. Rixner, W. J. Dally, B. Khailany, P. Mattson, U. J. Kapasi, and J. D. Owens, “Register Organization for Media Processing,” in Proc. HPCA, 2000, pp. 375–386.
5. 5. A. Terechko, E. L. Thenaff, M. Garg, J. Eijndhoven and H. Corporaal, “Inter-Cluster Communication Models for Clustered VLIW Processors,” in Proc. HPCA, 2003, pp. 354–364.
6. 6. T. J. Lin P. C. Hsiao C. W. Liu C. W. Jen 2006 Area-Efficient Register Organization for Fully-Synthesizable VLIW DSP Cores Int. J. Electr. Eng. 13 117 127 T. J. Lin, P. C. Hsiao, C. W. Liu, and C. W. Jen, “Area-Efficient Register Organization for Fully-Synthesizable VLIW DSP Cores,” Int. J. Electr. Eng., vol. 13, pp. 117–127, May 2006.
7. 7. P. Faraboschi, G. Brown, J. A. Fisher, G. Desoll and F. M. O. Homewood, “Lx: A Technology Platform for Customizable VLIW Embedded Processing,” in Proc. ISCA, 2000, pp. 203–213.
8. 8. G. G. Pechanek and S. Vassiliadis, “The ManArray Embedded Processor Architecture,” in Proc. Euromicro Conf., 2000, pp. 348–355.
9. 9. TMS320C64x DSP Generation. http://www.ti.com.
10. 10. K. Arora, H. Sharangpani, and R. Gupta, “Copied Register Files for Data Processors Having Many Execution Units,” US Patent 6,629,232, Sep. 30, 2003.
11. 11. A. Kowalczyk 2001 The First MAJC microprocessor: A Dual CPU System-On-a-Chip IEEE J. Solid-State Circuits 36 1609 1616 10.1109/4.962280 A. Kowalczyk et al., “The First MAJC Microprocessor: A Dual CPU System-On-a-Chip,” IEEE J. Solid-State Circuits, vol. 36, pp. 1609–1616, Nov. 2001.
12. 12. T. J. Lin et al., “Performance Evaluation of Ring-Structure Register File in Multimedia Applications,” in Proc. ICME, July 2003.
13. 13. A. V. Oppenheim, R. W. Schafer, and J. R. Buck, “Discrete-Time Signal Processing, 2nd ed.,” Prentice Hall, 1999.
14. 14. Independent JPEG Group. http://www.ijg.org.
15. 15. H. Pan and K. Asanovic, “Heads and Tails: A Variable-Length Instruction Format Supporting Parallel Fetch and Decode,” in Proc. CASES, 2001.
16. 16. T. Kumura, M. Ikekawa, M. Yoshida, and I. Kuroda, “VLIW DSP for Mobile Applications,” IEEE Signal Process. Mag., pp. 10–21, July 2002.
17. 17. G. Fettweis, M. Bolle, J. Kneip, and M. Weiss, “OnDSP: A New Architecture for Wireless LAN Applications,” Presented at Embedded Processor Forum, San Jose, 2002.
18. 18. T. J. Lin et al., “A Unified Processor Architecture for RISC & VLIW DSP,” in Proc. GLSVLSI, Apr. 2005.
19. 19. TMS320C55x DSP Generation. http://www.ti.com.
20. 20. R. K. Kolagotla et al., “High-Performance Dual-MAC DSP Architecture,” IEEE Signal Process. Mag., pp. 42–53, July 2002.
21. 21. J. P. Shen and M. H. Lipasti, “Modern Processor Design—Fundamental of Superscalar Processors,” McGraw-Hill, 2005.
22. 22. M. Keating and P. Bricaud, “Reuse Methodology Manual—For System-on-a-Chip Designs, 3rd ed.,” Kluwer, 2002.
23. 23. D. Chinnery and K. Keutzer, “Closing the Gap Between ASIC & Custom—Tools and Techniques for High-Performance ASIC Design,” Kluwer, 2002.
24. 24. J. Bhasker, “A SystemC Primer,” Star Galaxy Publishing, 2002.
25. 25. J. Bergeron, “Writing Testbenches—Functional Verification of HDL Models, 2nd ed.,” Kluwer, 2003.
26. 26. Versatile Platform Baseboard for ARM926EJ-S. http://www.arm.com/.
27. 27. I. E. G. Richardson, “H.264 and MPEG-4 Video Compression,” Wiley, 2003.
28. 28. J. L Hennessy and D. A. Patterson, Computer Architecture—A Quantitative Approach, 3rd ed.,” Morgan Kaufmann, 2002.
29. 29. W. B. Pennebaker and J. L. Mitchell, JPEG—Still Image Data Compression Standard, Van Nostrand Reinhold, 1993.
30. 30. Y. C. Lin, Y. P. You, and J. K. Lee, “Register Allocation for VLIW DSP Processors with Irregular Register Files,” in Proc. CPC, 2006.
31. 31. Intel 64 and IA-32 Architectures Software Developer’s Manual, Intel, Nov. 2006.
32. 32. The Thumb Architecture Extension. http://www.arm.com.